Systems and methods for reordering processor instructions

Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C712S225000

Reexamination Certificate

active

07634635

ABSTRACT:
Systems and methods for reordering processor instructions. In accordance with a first embodiment of the present invention, a microprocessor comprises circuitry to process an instruction extension, wherein the instruction extension is transparent to the programming model of the microprocessor. The instruction extension may comprise a field for indicating an offset from a memory structure pointer. The microprocessor includes circuitry for adding the offset to the memory structure pointer to indicate a specific element of the memory structure. The specific element of the memory structure comprises address information corresponding to speculative data.

REFERENCES:
patent: 5253349 (1993-10-01), Kreitzer
patent: 5269017 (1993-12-01), Hayden et al.
patent: 5274815 (1993-12-01), Trissel et al.
patent: 5349658 (1994-09-01), O'Rourke et al.
patent: 5421022 (1995-05-01), McKeen et al.
patent: 5454117 (1995-09-01), Puziol et al.
patent: 5467473 (1995-11-01), Kahle et al.
patent: 5511175 (1996-04-01), Favor
patent: 5519841 (1996-05-01), Sager et al.
patent: 5526499 (1996-06-01), Bernstein et al.
patent: 5537620 (1996-07-01), Breternitz, Jr.
patent: 5590295 (1996-12-01), Deosaran et al.
patent: 5625835 (1997-04-01), Ebcioglu et al.
patent: 5625837 (1997-04-01), Popescu et al.
patent: 5627981 (1997-05-01), Adler et al.
patent: 5751983 (1998-05-01), Abramson et al.
patent: 5754812 (1998-05-01), Favor et al.
patent: 5809273 (1998-09-01), Favor et al.
patent: 5832205 (1998-11-01), Kelly et al.
patent: 5875340 (1999-02-01), Quarnstrom et al.
patent: 5901308 (1999-05-01), Cohn et al.
patent: 5918005 (1999-06-01), Moreno et al.
patent: 5920710 (1999-07-01), Tan et al.
patent: 5931957 (1999-08-01), Konigsburg et al.
patent: 6011908 (2000-01-01), Wing et al.
patent: 6031992 (2000-02-01), Cmelik et al.
patent: 6065115 (2000-05-01), Sharangpani et al.
patent: 6141742 (2000-10-01), Favor
patent: 6148394 (2000-11-01), Tung et al.
patent: 6173366 (2001-01-01), Thayer et al.
patent: 6185668 (2001-02-01), Arya
patent: 6192465 (2001-02-01), Roberts
patent: 6202204 (2001-03-01), Wu et al.
patent: 6216200 (2001-04-01), Yeager
patent: 6463523 (2002-10-01), Kessler et al.
patent: 2003/0177340 (2003-09-01), Janik et al.
patent: 2324181 (1998-10-01), None
patent: WO98/28689 (1998-07-01), None
Gallagher, D. et al., Dynamic Memory Disambiguation etc., ASPLOS-VI Proceedings, Oct. 1994, pp. 1-13.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Systems and methods for reordering processor instructions does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Systems and methods for reordering processor instructions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods for reordering processor instructions will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4106961

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.