Electronic digital logic circuitry – Signal sensitivity or transmission integrity
Reexamination Certificate
2007-01-30
2007-01-30
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
C326S022000, C326S026000, C326S082000
Reexamination Certificate
active
11017265
ABSTRACT:
Systems and methods for reducing variations in the timing of signal transitions which may result from interference with neighboring signal lines by adjusting the drivability of in-line buffers based upon the hostile/friendly condition of the neighboring lines. In one embodiment, a first inverter includes selectable current paths between the buffer output and Vdd/ground. A higher current is selected for one path and a lower current is selected for the other path so that the buffer output will be pulled more strongly in the direction (Vdd/ground) to which the neighboring signals may be hostile. In one embodiment, each selectable current path includes a plurality of parallel transistors, one of which is always switched on and the others of which are switched on or off according to the friendly/hostile states of the neighboring signals.
REFERENCES:
patent: 6466486 (2002-10-01), Kawasumi
patent: 6803790 (2004-10-01), Haycock et al.
patent: 6922079 (2005-07-01), Drapkin et al.
Chadrakasan et al; “Design of High-Performance Microprocessor Circuits”; Problems and Solutions Regarding Capacitance; pp. 359-364; vol. 17.3, 2001 no month.
Kabushiki Kaisha Toshiba
Law Offices of Mark L. Berrier
Tran Anh Q.
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