Systems and methods for reducing the effect of noise while...

Static information storage and retrieval – Read/write circuit – Noise suppression

Reexamination Certificate

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Details

C365S207000, C365S189011, C365S158000

Reexamination Certificate

active

06678197

ABSTRACT:

TECHNICAL FIELD
The present invention is generally related to memory in the computer arts and, more particularly, is related to systems and methods for reducing the effect of noise while reading data from memory.
BACKGROUND OF THE INVENTION
Magneto-resistive devices such as a magnetic random access memory (MRAM) and a write-once memory store data. The magneto-resistive devices include memory cells and each memory cell stores a data “1” or a data “0”. Each memory cell of the magneto-resistive device includes a soft layer that is located above or below a tunneling junction and a hard layer that is located opposite to the soft layer.
Typically, a high gain sense amplifier is used to read data from each memory cell of the magneto-resistive device. Unfortunately, the high gain sense amplifier is subject to noise while reading the data since the high gain sense amplifier is built from circuits that are subject to alternating current (AC) noise, power supply noise, coupled digital switching noise, and noise associated with small area of the magneto-resistive device.
Signal-to-noise ratio (SNR) of the high gain sense amplifier is optimized to offset the effect of the noise that the high gain sense amplifier is subject to. Optimization of the SNR generally results in increased costs or being unable to meet SNR specifications of the computer arts since noise-reduction techniques are used to optimize signal-to-noise ratio (SNR) of the high gain sense amplifier. Examples of noise-reduction techniques include low noise design and physical layout techniques. Noise reduction techniques probably result in increased costs or not being able to meet the SNR specifications. Increased costs are because of increased complexity of a circuit executing one of the noise-reduction techniques, increased physical area occupied by the circuit, or increased cost of executing one of the noise-reduction techniques. Hence, optimizing the SNR probably results in increased costs or being unable to meet the SNR specifications.
A need exists in the industry to overcome the above-mentioned inadequacies of increased costs or being unable to meet the SNR specifications or other inadequacies or deficiencies.
SUMMARY OF THE INVENTION
The present invention provides systems and methods for reducing the effect of noise while reading data from memory.
Briefly described, in architecture, one embodiment of the system can be implemented as follows: a memory cell that stores a first data; multiple sensing devices that receive the first data and provide a first set of outputs; and a voting system that evaluates the first set of outputs to determine whether one of the outputs of the first set is valid data from the memory cell.
The present invention can also be viewed as providing methods for reducing the effect of noise while reading data from memory. In this regard, one embodiment of such a method, among others, can be broadly summarized by the following steps: reading data in parallel that is stored in a memory cell to provide outputs; and evaluating the outputs to determine whether one of the outputs is valid data from the memory cell.


REFERENCES:
patent: 6188615 (2001-02-01), Perner et al.
patent: 6191972 (2001-02-01), Miura et al.
patent: 6256224 (2001-07-01), Perner et al.
patent: 6462979 (2002-10-01), Schlosser et al.
patent: 6587371 (2003-07-01), Hidaka
patent: 2003/0123281 (2003-07-01), Iwata et al.
Scheuerlein, Roy; Gallagher, William; Parkin, Stuart; Lee, Alex; Ray, Sam; Robertazzi, Ray; Reohr, William, “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell” 2000 IEEE International Solid-State Circuits Conference, 8 pgs.
Durlam, M.; Naji, P.; DeHerrera, M.; Tehrani, S.; Kerszykow ski, G.; Kyler, K.; “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, 2000 IEEE International Solid-State Circuits Conference, 7 pgs.

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