Systems and methods for reducing testing times on integrated...

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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Reexamination Certificate

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07492179

ABSTRACT:
Disclosed herein are various embodiments of systems and method for testing dies on semiconductor wafers that reduce testing times on future wafers. The disclosed systems and methods may be employed to determine which BINs, if any, should be reprobed during a second testing pass. Specifically, the disclosed principles provide this determination based on the relationship between the yield recovery rate of a single BIN in view of the recovery rate for all BINs on the wafer, and the reprobe rate of that single BIN in view of the reprobe rate for all of the BINs. With this approach, both the recovery rate and the reprobe rate for a single BIN are evaluated as a percentage of the recovery rate or reprobe rate for all of the BINs on the wafer.

REFERENCES:
patent: 7212580 (2007-05-01), Hietala et al.
patent: 7253650 (2007-08-01), Balchiunas
patent: 2004/0204858 (2004-10-01), Brumbaugh
patent: 2007/0007981 (2007-01-01), Golan
Anthony T. McCray, James McNames, and David Abercrombie, Locating Disturbances in Semiconductor Manufacturing With Stepwise Regression, Aug. 2005, IEEE Transactions on semiconductror Manufacturing, vol. 18, No. 3, pp. 458-468.
Balchiunas, Akiko, “Increasing Productivity at Wafer Test Using Probe Data Analysis,” IBM Microelectronics, Jun. 8, 2004.

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