Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2006-12-19
2008-12-16
Du, Thuan N (Department: 2116)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S300000
Reexamination Certificate
active
07467314
ABSTRACT:
A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.
REFERENCES:
patent: 5880620 (1999-03-01), Gitlin et al.
patent: 6407576 (2002-06-01), Ngai et al.
patent: 6621325 (2003-09-01), Hart et al.
patent: 6744301 (2004-06-01), Tschanz et al.
patent: 6777978 (2004-08-01), Hart et al.
patent: 6930510 (2005-08-01), New
patent: 6980026 (2005-12-01), Trimberger
patent: 7188266 (2007-03-01), Mendel et al.
Jason H. Anderson and Farid N. Najm, “A Novel Low-Power FPGA Routing Switch” (2004) (unpublished, submitted to the 2004 IEEE Custom Integrated Circuits Conference, Orlando, Florida, Oct. 3-6, 2004).
Jason H. Anderson et al., “Active Leakage Power Optimization for FPGAs”, 2004 ACM/SIGDA Twelfth International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 33-41 (Feb. 22-24, 2004).
Jason H. Anderson and Farid N. Najm, “Low-Power Programmable Routing Circuitry for FPGAs” (2004) (unpublished, submitted to the 2004 International Conference on Computer Aided Design, San Jose, California, Nov. 7-11, 2004).
Deming Chen and Jason Cong, “Low-Power Technology Mapping for FPGA Architectures with Dual Supply Voltages”, 2004 ACM/SIGDA Twelfth International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 109-117 (Feb. 22-24, 2004).
A. Gayasen et al., “Reducing Leakage Energy in FPGAs Using Region-Constrained Placement”, 2004 ACM/SIGDA Twelfth International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 51-58 (Feb. 22-24, 2004).
Fei Li et al., “Low-Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics”, 2004 ACM/SIGDA Twelfth International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 42-50 (Feb. 22-24, 2004).
Fei Li et al., “FPGA Power Reduction Using Configurable Dual-Vdd”, 2004 Design Automation Conference, San Diego, California, pp. 735-740 (Jun. 7-11, 2004).
Arifur Rahman and Vijay Polavarapuv, “Evaluation of Low-Leakage Design Techniques for Field Programmable Gate Arrays”, 2004 ACM/SIGDA Twelfth International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 23-30 (Feb. 22-24, 2004).
“Mercury Programmable Logic Device Family”, Data Sheet, Version 2.2, Altera Corporation, pp. 17-28 (Jan. 2003).
Betz Vaughn
Mendel David
Altera Corporation
Brown Michael J
Du Thuan N
Mack Brian E.
Ropes & Gray LLP
LandOfFree
Systems and methods for reducing static and total power... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Systems and methods for reducing static and total power..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods for reducing static and total power... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4028174