Systems and methods for reducing IR-drop noise

Details Systems and methods for reducing IR-drop noise Systems and methods for reducing IR-drop noise

2006-11-14

2006-11-14

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07137089

ABSTRACT:
The diffusion structures in CMOS devices can be changed to minimize the effects of IR drop on those devices. A simulation can be run before tape-off to determine which transistors are at risk. The area of the source region and/or the width of the drain region of the at-risk transistor(s) can be adjusted to change the capacitive and/or resistive capability of the transistor(s). These altered diffusion structures can reduce the peak IR drop value, such as by an amount in the range of 8%–30% of the original peak noise, to prevent the chip from malfunctioning due to the resultant noise. The reduction in IR drop can be balanced with the timing delays introduced by the increased capacitance of the source area. An optimal combination of source area and drain width can be obtained and instituted during the simulation and testing processes.

REFERENCES:
patent: 5510999 (1996-04-01), Lee et al.
patent: 6209122 (2001-03-01), Jyu et al.
patent: 6671862 (2003-12-01), Seward

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