Systems and methods for reduced test case generation

Details Systems and methods for reduced test case generation Systems and methods for reduced test case generation

2007-05-30

2011-11-22

Memula, Suresh (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S136000

Reexamination Certificate

active

08065640

ABSTRACT:
In one embodiment of the invention, a method is disclosed including executing one or more commands of a work script to perform work on a portion of a netlist of an integrated circuit design; receiving an indication of a program fault in a first integrated circuit (IC) design program performing work on the portion of the netlist in response to the one or more commands of the work script; and generating a debug work script associated with the work script in response to the program fault, the debug work script including an identification of the portion of the netlist of the integrated circuit design upon which work was being performed during the program fault.

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