Systems and methods for reduced complexity LDPC decoding

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique

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Reexamination Certificate

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07900126

ABSTRACT:
Systems and methods for generating check node updates in the decoding of low-density parity-check (LDPC) codes use new approximations in order to reduce the complexity of implementing a LDPC decoder, while maintaining accuracy. The new approximations approximate the standard float-point sum-product algorithm (SPA), and can reduce the approximation error of min-sum algorithm (MSA) and have almost the same performance under 5 bits fix-point realization as the float-point sum-product algorithm (SPA).

REFERENCES:
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patent: 2006/0236195 (2006-10-01), Novichkov et al.
patent: 2007/0094568 (2007-04-01), Choi et al.
patent: 1698272 (2005-11-01), None
patent: 1798281 (2006-07-01), None
Papharalabos et al. Modified sum-product algorithms for decoding low-density parity-check codes. Apr. 3, 2006. Institution of engineering and Technology 2007. pp. 294-300.
Masera et al. Finite precision implementation of LDPC decoders. May 4, 2005. IEE proceedings online No. 20050205. pp. 1098-1102.

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