Systems and methods for reduced complexity LDPC decoding

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S752000

Reexamination Certificate

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07895500

ABSTRACT:
Systems and methods for generating check node updates in the decoding of low-density parity-check (LDPC) codes use new approximations in order to reduce the complexity of implementing a LDPC decoder, while maintaining accuracy. The new approximations approximate the standard sum-product algorithm (SPA), and can reduce the approximation error of min-sum algorithm (MSA) and have almost the same performance as sum-product algorithm (SPA) under both floating precision operation and fixed-point operation.

REFERENCES:
patent: 6539367 (2003-03-01), Blanksby et al.
patent: 7454685 (2008-11-01), Kim et al.
patent: 7458009 (2008-11-01), Yu et al.
patent: 7747934 (2010-06-01), Livshitz
patent: 2003/0229843 (2003-12-01), Yu et al.
patent: 2006/0236195 (2006-10-01), Novichkov et al.
patent: 2008/0104474 (2008-05-01), Gao et al.

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