Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-12-12
2006-12-12
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S756000, C714S769000, C714S784000
Reexamination Certificate
active
07149945
ABSTRACT:
In one embodiment, a memory controller comprises a cache line processing block for processing a cache line into a plurality of segments, an error correction code (ECC) generation block that forms ECC code words for each of the plurality of segments for storage in a plurality of memory components, an ECC correction block for correcting at least one single-byte erasure error in each erasure corrupted ECC code word retrieved from the plurality of memory components, and an error seeding block that enables a respective error to be inserted into each ECC code word of the cache line in response to a plurality of error registers.
REFERENCES:
patent: 4612640 (1986-09-01), Mehrotra et al.
patent: 7103824 (2006-09-01), Halford
U.S. Appl. No. 10/435,150, C. M. Brueggen.
Kaneda, Shigeo, et al., “Single Byte Error Correcting-Double Byte Detecting Codes for Memory Systems.” IEEE Transactions on Computers, vol. C-3, No. 7, Jul. 1982, pp. 596-602.
Morelos-Zaragoza, Robert H., “The Art of Error Correcting Coding.” Sony Computer Science Laboratories, Inc. Japan, pp. 33-72.
Hewlett--Packard Development Company, L.P.
Lamarre Guy J.
LandOfFree
Systems and methods for providing error correction code... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Systems and methods for providing error correction code..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods for providing error correction code... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3703792