Systems and methods for performing clock gating checks

Details Systems and methods for performing clock gating checks Systems and methods for performing clock gating checks

2002-06-05

2004-10-19

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C327S145000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06807658

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to computer-aided circuit design systems, and more particularly to a clock gating check system and method for performing clock gating checks on logic cells.
2. Discussion of the Related Art
Integrated circuits (ICs) are electrical circuits comprising transistors, resistors, capacitors, and other components on a single semiconductor “chip” in which the components are interconnected to perform a variety of functions. Typical examples of ICs include, microprocessors, programmable logic devices (PLDs), electrically erasable programmable read only memory devices (EEPROMs), random access memory devices (RAMs), operational amplifiers and voltage regulators. A circuit designer typically designs the IC by creating a circuit schematic indicating the electrical components and their interconnections. Often, designs are simulated by computer to verify functionality and to ensure that performance goals are satisfied.
In electrical device engineering, the design and analysis work involved in producing electronic devices is often performed using electronic computer-aided design (E-CAD) tools. As will be appreciated, electronic devices include analog, digital, mixed hardware, optical, electromechanical, and a variety of other electrical devices. The design and subsequent simulation of any circuit, very large scale integration (VLSI) chip, or other electrical device via E-CAD tools allows a product to be thoroughly tested and often eliminates the need for building a prototype. Thus, today's sophisticated E-CAD tools may enable the circuit manufacturer to go directly to the manufacturing stage without having to perform costly, time consuming prototyping.
In order to perform the simulation and analysis of a hardware device, E-CAD tools utilize an electronic representation of the hardware device. A “netlist” is one common electronic representation of a hardware device. As will be appreciated by those skilled in the art of hardware device design, a “netlist” is a detailed circuit specification used by logic synthesizers, circuit simulators and other circuit design optimization tools. A netlist typically comprises a list of circuit components and the interconnections between those components.
The two forms of a netlist are the flat netlist and the hierarchical netlist. Often, a netlist will contain a number of circuit “modules,” which are used repetitively throughout the larger circuit. A flat netlist will contain multiple copies of the circuit modules essentially containing no boundary differentiation between the circuit modules and other components in the device. By way of analogy, a graphical representation of a flat netlist is the schematic of the circuit device.
In contrast, a hierarchical netlist will only maintain one copy of a circuit module, which may be used in multiple locations. By way of analogy, a graphical representation of a hierarchical netlist shows the basic and/or non-repetitive devices in schematic form and the more complex and/or repetitive circuit modules are represented by “black boxes.” As will be appreciated by those skilled in the art, a black box is a system or component whose inputs, outputs, and general function of which are known, but the contents of which are not shown. These “black box” representations, hereinafter called “modules,” will mask the complexities therein, typically showing only input/output ports.
An IC design can be represented at different levels of abstraction, such as at the register-transfer level (RTL) and at the logic level, using a hardware description language (HDL). VHDL® and Verilog® are examples of HDL languages. At any abstraction level, an IC design is specified using behavioral or structural descriptions, or a mix of both. At the logical level, the behavioral description is specified using Boolean equations. The structural description is represented as a netlist of primitive cells. Examples of primitive cells are, among others, full-adders, logic gates, latches, and flip-flops.
Set forth above is some very basic information regarding integrated circuits and circuit schematics that are represented in netlists. Systems are presently known that use the information provided in netlists to evaluate circuit timing and other related parameters. More specifically, systems are known that perform a timing analysis of circuits using netlist files. Although the operational specifics may vary from system to system, such systems generally operate by identifying certain critical timing paths, and then evaluating the circuit to determine whether timing violations occur through the critical paths. As is known, timing specifications may be provided to such systems by way of a configuration file.
FIG. 1A
is a block diagram of a static timing analyzer system
2
, as is known in the prior art. Specifically, some examples of system
2
are marketed under the name Primetime® and Pathmill®.
FIG. 1A
illustrates the informational flow in a system
2
. At the center of the diagram is a static timing analyzer
10
, (i.e., the Primetime® program). Surrounding this block
10
are a number of other blocks that represent various input and output files and/or information.
More particularly, the static timing analyzer
10
may utilize a configuration file
12
, a file of timing models
14
, one or more netlist files
16
, a technology file
18
, and a parasitics file
20
, for various input information. In addition, the static timing analyzer
10
may generate a number of different output files or other output information, including a critical path report
22
, a runtime log file
24
, an error report
26
, and a software interface file
28
. When started, the static timing analyzer
10
first processes the input netlist file(s)
16
, the technology file
18
, and the configuration files
12
. The information from these files is subsequently used for performing path analyses. The function and operation of the static timing analyzer
10
are generally well known, and therefore need not be discussed in detail herein.
While tools such as these are useful for the design verification process after layout, there are various shortcomings in the static timing analyzer
10
, and other similar products. These shortcomings include, but are not limited to, performing accurate clock gating checks on logic cells during static timing. Problems with clock gating occur when a logic cell is used to turn a clock on or off based upon other logic signals. One problem occurs when the clock signal changes state at or near the same time that the logic signal changes state as to create what is referred to as a timing “glitch.” These timing glitches can cause erroneous circuit operations. The most common method for preventing glitches is a clock gating check. It is nearly impossible to perform a clock gating check manually in a large design because a large design may have tens of thousands of logic cells each requiring a clock gating check.
The clock gating check ensures that the clock transition does not too closely precede or follow a change in the gating signal
43
. This is shown in
FIG. 1B
, where the clock signal
42
and gating signal
43
are input into logic cell
41
, and the output of logic cell
41
is the output signal
48
. As stated above, the clock gating check makes sure that the transition of the clock signal
42
does not too closely precede or follow a transition in the gating signal
43
, thereby creating glitches on the output signal
48
. A comparison of these signals illustrating the potential problem is illustrated in FIG.
1
C. First, the clock signal
42
has a clock transition time
44
that is approximately equal to the gating signal transition time
46
of the gating signal
43
. This input of the clock signal
42
and the gating signal
43
into logic cell
41
can create an output signal
48
with a glitch
49
.
Clock gating checks usually include a safety margin factor or buffer time period that is set at the time of the static timing analysis. This buffer time pe

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