Systems and methods for overlay shift determination

Details Systems and methods for overlay shift determination Systems and methods for overlay shift determination

2006-04-12

2009-06-23

Pert, Evan (Department: 2826)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

C700S121000

Reexamination Certificate

active

07550303

ABSTRACT:
Method for measuring misalignment between at least two layers of an integrated circuit. The method includes applying a current between a plurality of probe members in a first layer, wherein a first probe member and a second probe member of the plurality of probe members are substantially aligned along a first axis and partially overlap an overlay target in a second layer, measuring a voltage across the plurality of probe members wherein at least a voltage across the first probe member and a third probe member disposed perpendicular to the first axis and a voltage across the second probe member and the third probe member are measured, and determining an amount of misalignment between the first layer and the second layer along at least one of the first axis and the second axis based on the measuring steps.

REFERENCES:
patent: 4347479 (1982-08-01), Cullet
patent: 4386459 (1983-06-01), Boulin
patent: 4399205 (1983-08-01), Bergendahl
patent: 4437760 (1984-03-01), Ausschnitt
patent: 4475811 (1984-10-01), Brunner
patent: 4538105 (1985-08-01), Ausschnitt
patent: 4571538 (1986-02-01), Chow
patent: 5082792 (1992-01-01), Pasch et al.
patent: 5247262 (1993-09-01), Cresswell et al.
patent: 5383136 (1995-01-01), Cresswell et al.
patent: 5390420 (1995-02-01), Schultz
patent: 5648661 (1997-07-01), Rostoker et al.
patent: 5699282 (1997-12-01), Allen et al.
patent: 5770995 (1998-06-01), Kamiya
patent: 5998226 (1999-12-01), Chan
patent: 6080597 (2000-06-01), Moon
patent: 6242757 (2001-06-01), Tzeng et al.
patent: 6380554 (2002-04-01), Bush et al.
patent: 6383827 (2002-05-01), Lukanc et al.
patent: 6393714 (2002-05-01), Look et al.
patent: 6423555 (2002-07-01), Babcock
patent: 6623996 (2003-09-01), Nanba
patent: 6716653 (2004-04-01), Look et al.
patent: 2005445 (1990-01-01), None
patent: 4032216 (1992-02-01), None
Publication: Hybrid Optical-Electrical Overlay Test Structure [for CMOS], Cresswell, M.W. et al., Microelectronic Test Structures, 1996. Proceedings. 1996 IEEE International Conference on Mar. 25, 1996.
Kern Rim et al., “Transconductance Enhancement in Deep Submicron Strained-Si n-MOSFETs” International Electron Devices Meeting, 26, 8, 1, IEEE, Sep. 1998.
Kern Rim et al., “Characteristics and Device Design of Sub-100nm Strained Si N-and PMOSFETs” 2002 Symposium On VLSI Technology Digest of Technical Papers, IEEE, pp. 98-99.
Gregory Scott, et al., “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress”, International Electron Devices Meeting, 34.4.1, IEEE, Sep. 1999.
F. Ootsuka, et al., “A Highly Dense, High-Performance 130nm node CMOS Technology for Large Scale System-on-a Chip Application”, International Electron Devices Meeting, 23.5.1, IEEE, Apr. 2000.
Shinya Ito, et al., “Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design”, International Electron Devices Meeting, 10.7.1, IEEE, Apr. 2000.
A. Shimizu, et al., “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement”, International Electron Devices Meeting, IEEE, Mar. 2001.
K. Ota, et al., Novel Locally Strained Channel Technique for high Performance 55nm CMOS, International Electron Devices Meeting, 2.2.1, IEEE, Feb. 2002.
D.S. Perloff, “A Van der Pauw structure for determining mask superposition errors on semiconductor slices”, Solid State Electronics 21, Aug. 1978, pp. 1013-1018.
D.H. Leebrick et al., “An Electrical Alignment Test Device and Its Use in Investigating Processing Parameters”, Kodak Microelectronics Seminar proceedings, interface '77, Oct. 1977, pp. 66-83.
T.J. Russel et al., A Comparison of Electrical and Visual Alignment test Structures for Evaluating Photomask Alignment in Integrated Circuit Manufacturing, International Electron Devices Meeting, Dec. 1977, pp. 7A to 7F.
D.R. Thomas et al., “An Electrical Photolithographic Alignment Monitor”, IBM disclosure in 1974 Government Microcircuit Applications Conference: digest of papers, pp. 196-197.

Affiliated with

Also associated with

Rating

Systems and methods for overlay shift determination does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Systems and methods for overlay shift determination, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods for overlay shift determination will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4054112