Systems and methods for multiprocessor scalable write barrier

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C707S793000, C709S241000

Reexamination Certificate

active

06973554

ABSTRACT:
Systems and methods providing a multiprocessor scalable write barrier to a main memory card table are described. The main memory is divided into multiple cards bit-mapped by the card table. In one aspect, an application store operation (reference) associated with one of the cards is detected. Responsive to detecting the reference, card table bit(s) that are mapped to the card are evaluated. Responsive to determining that the bit(s) have already been marked as dirty, the card table bit(s) are not again marked. This technique effectively reduces the probability of more than a single overlapping write operation to a card table cache line by two or more processors in the system.

REFERENCES:
patent: 4296476 (1981-10-01), Mayer et al.
patent: 4432067 (1984-02-01), Nielsen
patent: 4905280 (1990-02-01), Wiedemer
patent: 5382983 (1995-01-01), Kwoh et al.
patent: 5459487 (1995-10-01), Bouton
patent: 5550575 (1996-08-01), West et al.
patent: 5551701 (1996-09-01), Bouton et al.
patent: 5558339 (1996-09-01), Perlman
patent: 5592651 (1997-01-01), Rackman
patent: 5598276 (1997-01-01), Cookson et al.
patent: 5634849 (1997-06-01), Abecassis
patent: 5649862 (1997-07-01), Sakaguchi et al.
patent: 5716273 (1998-02-01), Yuen
patent: 5752883 (1998-05-01), Butcher et al.
patent: 5791992 (1998-08-01), Crump et al.
patent: 5876286 (1999-03-01), Lee
patent: 5878134 (1999-03-01), Handelman et al.
patent: 5896125 (1999-04-01), Niedzwiecki
patent: 5917256 (1999-06-01), Broadbent, II
patent: 5969283 (1999-10-01), Looney et al.
patent: 5973683 (1999-10-01), Cragun et al.
patent: 5978920 (1999-11-01), Lee
patent: 5993319 (1999-11-01), Aoyama
patent: 6001015 (1999-12-01), Nishiumi et al.
patent: 6009433 (1999-12-01), Kurano et al.
patent: 6025869 (2000-02-01), Stas et al.
patent: 6049810 (2000-04-01), Schwartz et al.
patent: 6065020 (2000-05-01), Dussud
patent: 6115079 (2000-09-01), McRae
patent: 6115782 (2000-09-01), Wolczko et al.
patent: 6148309 (2000-11-01), Azagury et al.
patent: 6148310 (2000-11-01), Azagury et al.
patent: 6161185 (2000-12-01), Guthrie et al.
patent: 6173294 (2001-01-01), Azagury et al.
patent: 6224485 (2001-05-01), Dickinson et al.
patent: 6226653 (2001-05-01), Alpern et al.
patent: 6230320 (2001-05-01), Gakumura
patent: 6280327 (2001-08-01), Leifer et al.
patent: 6280329 (2001-08-01), Kondo et al.
patent: 6298441 (2001-10-01), Handelman et al.
patent: 6299535 (2001-10-01), Tanaka
patent: 6309301 (2001-10-01), Sano
patent: 6312336 (2001-11-01), Handelman et al.
patent: 6317756 (2001-11-01), Kolodner et al.
patent: 6320320 (2001-11-01), Bailey, III et al.
patent: 6393430 (2002-05-01), Van Ryzin
patent: 6396531 (2002-05-01), Gerszberg et al.
patent: 6464585 (2002-10-01), Miyamoto et al.
patent: 6468160 (2002-10-01), Eliott
patent: 6470361 (2002-10-01), Alpern et al.
patent: 6490599 (2002-12-01), Kolodner et al.
patent: 6502111 (2002-12-01), Dussud
patent: 6510440 (2003-01-01), Alpern et al.
patent: 6520890 (2003-02-01), Hsu
patent: 6535269 (2003-03-01), Sherman et al.
patent: 6599194 (2003-07-01), Smith et al.
patent: 6601171 (2003-07-01), Carter et al.
patent: 6712704 (2004-03-01), Eliott
patent: 6769989 (2004-08-01), Smith et al.
patent: 6845347 (2005-01-01), Yang et al.
patent: 2001/0004609 (2001-06-01), Walker et al.
patent: 2002/0077177 (2002-06-01), Elliott
patent: 2003/0008715 (2003-01-01), Huber et al.
patent: 2003/0008751 (2003-01-01), Hsu
patent: 2004/0162137 (2004-08-01), Scott
patent: 2004/0187102 (2004-09-01), Garthwaite
patent: 10046437 (2002-04-01), None
patent: 0809214 (1997-11-01), None
patent: 0889420 (1999-01-01), None
patent: 0998966 (2000-05-01), None
patent: 1035706 (2000-09-01), None
patent: 1126425 (2001-08-01), None
patent: 2743434 (1997-07-01), None
patent: WO 98/48353 (1998-10-01), None
patent: WO 00/40027 (2000-07-01), None
patent: WO 00/51036 (2000-08-01), None
patent: WO 01/05477 (2001-01-01), None
patent: WO 01/08148 (2001-02-01), None
patent: WO 01/84768 (2001-11-01), None
A. Hosking, J. Moss, D. Stefanovic, “A Comparative Performance Evaluation of Write Barrier Implementations,” p. 1-18, Proceedings ACM Conference on Object-Oriented Programming Systems, Languages, & Applications; Vancouver, Canada, Oct. 1992, p 92-109.
“Parallet Garbage Collection for shared Memory Multiprocessors”, Flood, Detlefs, Shavit, Zhang, USENIX Java Virtual Machine Research & Technology Symposium, Apr. 23-24, 2001. California, USA.
Hosking, A.L., et al., “Remembered Sets Can Also Play Cards,” OOPSLA '93, Workshop on Garbage Collection and Memory Management, Washington D.C., Sep. 1993.
Wilson, P.R., “A Card-Marking Scheme for Controlling Intergenerational References in Generation-Based Garbage Collection on Stock Hardware,” ACM SIGPLAN Notices, 24-5:87-92 (1989).
Yang, et al.; “Java Virtual Memory Timing Probes: A Study of Object Life Span and Garbage Collection” Conference Proceedings of the IEEE International Performance Computing and Communications, Apr. 2002, pp. 73-80.
Wise et al.; “Research Demonstration of a Hardware Reference-Countying Heap” LISP and Symbolic Computation vol. 10 No. 2, Jul. 1997, pp. 159-181.
Chang et al.; “DMMX: Dynamic Memory Management Extensions” Journal of Systems and Software, vol. 63 No. 3, Sep. 2002, pp. 187-199.
SRISA-AN et al.; “Object Resizing and Reclamation Through the Use of Hardware Bit-Maps” Microprocessors and Microsystems vol. 25 No. 9-10, Jan. 2002, pp. 459-467.
Levanoni et al.; “An On-the Fly Reference Counting Garbage Collector for Java” ACM Sigplan Notices vol. 36 No. 11, Nov. 2001, pp. 367-380.
Ossia et al.; “A Parallel Incremental and Concurrent GC for Servers” ACM Sigplan Notices vol. 27 No. 5, May 2002, pp. 129-140.
Kwon et al.; “Java Garbage Collection for a Small Interactive System” Journal of Korean Information Science Society vol. 29 No. 11-12, Dec. 2002, pp. 957-965.
“Xbox to Deliver Ultimate Console Gaming Experience” San Jose CA, Mar. 10, 2000, 3 pages.
Bloomberg News “U.S. version of Playstation2 to have modem hard drive”, c
et News.com, Apr. 14, 2000; 2 pages.
Gordon, C.; “Interviews-John Gildred ofIndrema on the L600” Planet GeForce, Oct. 19, 2000 5 pages.
IGN.com, “What is the 64DD?”; IGN.com; Sep. 17, 1997; 9 pages.
IGN.com, “The 64DD: Nintendo's Disk Drive -Everything you ever wanted to know about the N64's first major add-on” IGN.com; Jan. 28, 1998; 7 pages.
IGN.com, “The 64DD Connection—Here's how the 64DD and the Nintendo 64 connect”; IGN.com; Oct. 20, 1999; 5 pages.
IGN.com, “IGN64's Ultimate 64DD FAQ—Everything you ever wanted to know about the upcoming disk drive add-on” IGN.com; Dec. 15, 1999; 12 pages.
Fedor, J., Johnson, S., Carver, B.; “Links 386CD, Players Manual”; Access Software Inc. Jan. 1, 1995; pp. 1-87.
Lehrbaum, Rick, “Linux fuels game console plus” ZDNet, Jul. 17, 2000, 3 pages.
Takahashi, Dean; “Microsoft goes gaming (Prodict Development)” Electronic Businss, May 1, 2000, 2 pages.
Mowatt, Todd “Indrema: Linux-Based Console” Aug. 11, 2000; 2 pages.
Daily Radar.com; “Metropolis Street Racer Review”; Nov. 13, 2000; 5 pages.
SEGA Enterprises, Ltd., “Metropolis Street Racer”; User Manual, 2000, 18 pages.
Jones; Lins; “Garbage Collection”; pp. 171-173 “Inter-Generational Pointers”.
“CES: Bill Gates zeigt die Xbox” Golem.de 'Online! Jan. 6, 2000 Retrieved from the internet: url:http://dyn1.golem.de/cgi-bin/usisapi.d11/forprint??id=11561> retrieved Jun. 18, 2004; pp. 1-3.
“DFU Verbindung herstellen” FAQ, 'Online! XP002318226 Retrieved from the Internet: URL: www.purtec.de>retrieved on 2000!, 1 page.
“PlayStation 2 Instruction Manual” 'Online! 2000 Sony Computer Entertainment Retrieved from the internet: url:www.playstation.com. retrieved on Jun. 18, 2004; 28 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Systems and methods for multiprocessor scalable write barrier does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Systems and methods for multiprocessor scalable write barrier, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods for multiprocessor scalable write barrier will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3483899

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.