Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2001-10-04
2004-03-30
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C710S033000, C710S111000, C710S309000, C710S244000, C712S033000, C712S034000, C712S043000, C712S225000, C711S169000
Reexamination Certificate
active
06715042
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to data processing systems, and in particular, to data processing systems including multiple bus masters accessing common memory resources.
2. Description of the Related Art
Modern signal processing systems, such as those found, for example, in commercial and consumer audio and multimedia products, are moving, with improvements in Very Large Scale Integration (VLSI) fabrication processes, to “system on a chip” (SoC) implementations. Such implementations may include, as will be discussed further hereinbelow in conjunction with
FIG. 1
, one or more processors which may perform signal processing and control functions, on-chip memory, and signal amplification whereby an amplified signal may be delivered directly to the user's listening device, a speaker or a headphone set, for example.
As the sources of digital audio, video and multimedia data have become more sophisticated, the tasks required of the play back systems have correspondingly become more complex. For example, the source stream may be delivered in a compressed format in accordance with one or more standardized compression formats, such as those promulgated by the Motion Picture Experts Group (MPEG). Additionally, the compressed digital audio data may be embedded in a multiplexed bitstream that includes additional data, for example, conditional access information which may be used to limit the access to the underlying content to users who have subscribed thereto. Consequently, the digital signal processing demands placed upon the SoC may be significant. Thus, such an SoC may incorporate a DSP engine to perform the computationally intensive signal processing required to extract and recover the uncompressed digital data. Additionally, an SoC may include a general purpose microprocessor (&mgr;P) to provide control functionality (such as user input/output, for example, from a keypad or keyboard, or information display on an LCD device). Additionally, the SoC may include a memory controller for accessing an on-chip memory, or, alternatively, a combination of on-chip and off-chip memory, for storing processor instructions and data. The memory resources may be shared by the DSP engine and the microprocessor, creating potential memory resource contentions.
Consequently, there is a need in the art for systems and methods for shared memory access in a multimaster environment, and in particular a need for mechanisms to arbitrate between masters contending for the shared memory which admits switching between masters without losing data between transactions. Additionally, there is a need for an arbitration mechanism that mitgates against starvation of lower priority masters by a master having a predetermined higher priority.
SUMMARY OF THE INVENTION
According to the principles of the present invention, an amplifier system is disclosed. The system includes a first processor configured to decode a digital signal from a digital signal source, and a second processor configured to provide control signals to the first processor. A memory controller is configured to for communicating instructions and data between a memory device and the first and second processors. An expansion unit has a first port coupled to the first processor and a second port coupled to the second processor. The expansion unit includes a state generator with circuitry for selecting one of the first and second ports for receiving a memory device access grant in response to at least one request from a corresponding one of the first and second processor. The circuitry for selecting one of the first and second ports further contains circuitry for selecting the one of the first and second ports according to a selected arbitration protocol. A duration of the memory device access grant comprises one of a preselected number of accesses and a preselected timeslice The system also includes logic for selecting the one of the preselected number of accesses and the preselected timeslice for determining the duration of the memory device access grant. An amplifier is provided for amplifying a decoded digital signal from the first processor.
The inventive concept addresses a problem in multi-processor amplifier systems, namely access to common memory resources storing processor instructions and memory while mitigating the breaking of the data pipelines while switching between bus masters. Typical arbitration schemes designate a priority master, which can result in bus hogging, whereby bus masters having lower priority may be starved. In accordance with the present inventive principles, an access grant is allocated a duration selectably having a preselected timeslice or a preselected number of memory device accesses.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
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Hao Jun
Mirza Nadeem
Chace Christian P.
Cirrus Logic Inc.
Lin Steven
Newberger Barry S.
Sparks Donald
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