Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling
Reexamination Certificate
2006-05-30
2006-05-30
Banankhah, Majid (Department: 2195)
Electrical computers and digital processing systems: virtual mac
Task management or control
Process scheduling
C718S100000, C718S102000, C710S200000, C712S228000, C712S229000
Reexamination Certificate
active
07055151
ABSTRACT:
In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.
REFERENCES:
patent: 2686844 (1954-08-01), Brewer
patent: 4604694 (1986-08-01), Hough
patent: 4797816 (1989-01-01), Uchiyama et al.
patent: 4885744 (1989-12-01), Lespagnol et al.
patent: 5062106 (1991-10-01), Yamazaki
patent: 5175732 (1992-12-01), Hendel et al.
patent: 5233606 (1993-08-01), Pashan et al.
patent: 5261062 (1993-11-01), Sato
patent: 5311509 (1994-05-01), Heddes et al.
patent: 5337308 (1994-08-01), Fan
patent: 5357617 (1994-10-01), Davis et al.
patent: 5361337 (1994-11-01), Okin
patent: 5457687 (1995-10-01), Newman
patent: 5517495 (1996-05-01), Lund et al.
patent: 5528588 (1996-06-01), Bennett et al.
patent: 5541912 (1996-07-01), Choudhury et al.
patent: 5555264 (1996-09-01), Sallberg et al.
patent: 5557611 (1996-09-01), Cappellari et al.
patent: 5583863 (1996-12-01), Darr, Jr. et al.
patent: 5592476 (1997-01-01), Calamvokis et al.
patent: 5629928 (1997-05-01), Calvignac et al.
patent: 5633859 (1997-05-01), Jain et al.
patent: 5633867 (1997-05-01), Ben-Num et al.
patent: 5689508 (1997-11-01), Lyles
patent: 5704047 (1997-12-01), Schneeberger
patent: 5715250 (1998-02-01), Watanabe
patent: 5719853 (1998-02-01), Ikeda
patent: 5748629 (1998-05-01), Caldara et al.
patent: 5751951 (1998-05-01), Osborne et al.
patent: 5809024 (1998-09-01), Ferguson et al.
patent: 5838968 (1998-11-01), Culbert
patent: 6018759 (2000-01-01), Doing et al.
patent: 6591358 (2003-07-01), Jaffrey
patent: 3101551 (1991-04-01), None
patent: 10049390 (1998-02-01), None
patent: WO 95/20182 (1995-07-01), None
patent: WO 95/32570 (1995-11-01), None
Dynamic Instruction Stream Computer, Dr. Marion daniel Nemirovsky, Apple Computer Corporation, 1991.
“Structured Computer Organization”, Second Edition, “Andrew Tanenbaum”, 1984 by Prentic Hall.
Farrens M. K. et al.: “Strategies For Achieving Improved Processor Throughput”, Computer Architecture News, Association For Computing Machinery, New York, US, vol. 19, No. 3, May 1, 1991, pp. 362-369.
Lee E. A. et al: “Pipeline Interleaved Programmable DSP's: Architecture”, IEEE Transactions On Acoustics, Speech And Signal Processing, IEEE Inc. New York, US, vol. 35, No. 9, Sep. 1, 1987, pp. 1320-1333.
Nemirovsky M. D. et al.: “Disc: Dynamic Instruction Stream Computer”, Proceedings Of The Annual International Symposium On Microarchitecture, XX, XX, 1991, pp. 163-171.
Allyn Romanow et al. “Dynamics of TCP Traffic Over ATM Networks”IEEE Journal on Selected Areas in Communications, vol. 13, No. 4, pp. 633-541, May 1995.
Alan Demers et al. “Analysis and Simulation Of A Fair Queueing Algorithm” © 1989 ACM, pp. 1-12.
“ATMS2003B Switch Controller 1 “White””,MMC Networks, Dec. 1995, 32 pages.
Beraldi, R., et al: “Selective BECN Schemes for Congestion Control of ABR Traffic in ATM Lan”,1996 IEEE Int'l Conf. on Communications(ICC), Converging Technologies for Tomorrow's Applications, Dallas, Jun. 23-27, 1996. pp. 503-507.
Dutton, Harry, J.R. and Lenhard, Peter, “Asynchronous Transfer Mode (ATM) Technical Overview” (IBM, Prentice-Hall PTR, New Jersey, 1995), pp. 3-1 through 3-.
Flanagan, William A., “ATM (Asyncrhronous Transfer Mode) User's Guide,” (Flatiron Publishing, Inc. New York, 1994), pp. 25-49.
Hongqing Li et al. “A Simulation Study of TCP Performance in ATM Networks With ABR and UBR Services”Proceedings vol. 3, 1996 IEEE Infocom '96, Fifteenth Annual Joint Conference of the IEEE Computer and Communications Societies, Mar. 24-28, 1996, pp. v-xvi and pp. 1269-1276 (21 pages total including cover page).
Hongqing, Li, et al.: “Performance of TCP Over UBR Service in ATM Networks With Per-VC Early Packet Discard Schemes”Proceedings of the 1996 IEEE 15th Annual Int' Phoenix Conf. on Computers and Communication,Mar. 27-29, 1996, pp. 350-357.
Ozveren, C., et al: “Reliable and Efficient Hop-By-Hop Flow Control”,Computer Communications Review, vol. 24, No. 4, Oct. 1, 1994, pp. 89-100.
Tanenbaum, Andrew S., “Computer Networks” (Prentice Hall PTR, 3rd Ed., 1996) pp. 148-150.
Joffe Alexander
Vyshetsky Dmitry
Applied Micro Circuits Corporation
Banankhah Majid
MacPherson Kwok & Chen & Heid LLP
Shenker Michael
LandOfFree
Systems and methods for multi-tasking, resource sharing and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Systems and methods for multi-tasking, resource sharing and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods for multi-tasking, resource sharing and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3598706