Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-04-21
2008-10-28
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07444613
ABSTRACT:
Systems and methods are provided for mapping logic functions from logic elements (“LEs”) into synchronous embedded memory blocks (“EMBs”) of programmable logic devices (“PLDs”). This technique increases the amount of logic that can fit into the PLD. Where area savings are significant, smaller PLDs may be selected to implement a particular circuit. One aspect of the invention relates to methods for identifying sequential cones of logic that may be mapped into synchronous EMBs. After the sequential logic cones are identified for mapping into a synchronous EMB, the logic cone may be selected, expanded, restructured, and retimed, as necessary, to implement the mapping. Another aspect of the invention relates to techniques for handling architectural restrictions of synchronous EMBs, such as the inability to implement the asynchronous behavior of synchronous logic.
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Brown Stephen
Chiu Gordon
Manohararajah Valavan
Singh Deshanand
Altera Corporation
Chasan Michael J.
Garbowski Leigh Marie
Ropes & Gray LLP
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