Systems and methods for maintaining performance at a reduced...

Semiconductor device manufacturing: process – Forming schottky junction – Compound semiconductor

Reexamination Certificate

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Reexamination Certificate

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07811917

ABSTRACT:
Systems and methods are provided for maintaining performance of an integrated circuit at a reduced power. The systems and methods employ a performance monitor that generates a signal indicative of at least one performance characteristic of at least a portion of a critical path associated with the integrated circuit. The system further comprises a supply control that adjusts a supply voltage of the integrated circuit to maintain performance at a reduced power based on the signal. A temperature adjustment component can be provided to adjust the signal to compensate for temperature offsets associated with performance of the performance monitor relative to performance of the critical path over different operating temperatures. A performance measurement of the performance monitor can be determined based on the concurrent triggering of the performance monitor and the critical path.

REFERENCES:
patent: 6249002 (2001-06-01), Butler
patent: 6369712 (2002-04-01), Letkomiller et al.
patent: 6535798 (2003-03-01), Bhatia et al.
patent: 7239685 (2007-07-01), Petrick et al.
patent: 7451332 (2008-11-01), Culbert et al.

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