Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2011-04-19
2011-04-19
Chase, Shelly A (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
Reexamination Certificate
active
07930621
ABSTRACT:
Various embodiments of the present invention provide systems and methods for decoding encoded information. For example, a method for post processing error correction in a decoder system is disclosed. The method includes receiving and iteratively decoding a soft input to generate a hard output associated with the soft input. The method further includes post processing when a plurality of parity checks fail. At least one bit of the hard output is identified as being potentially incorrect. The identified bit is modified, and the plurality of parity checks is thereafter repeated.
REFERENCES:
patent: 5278846 (1994-01-01), Okayama et al.
patent: 5325402 (1994-06-01), Ushirokawa
patent: 5392299 (1995-02-01), Rhines et al.
patent: 5428646 (1995-06-01), Eyuboglu
patent: 5513192 (1996-04-01), Janku et al.
patent: 5612964 (1997-03-01), Haraszti
patent: 5701314 (1997-12-01), Armstrong et al.
patent: 5717706 (1998-02-01), Ikeda
patent: 5844945 (1998-12-01), Nam et al.
patent: 5898710 (1999-04-01), Amrany
patent: 5923713 (1999-07-01), Hatakeyama
patent: 5978414 (1999-11-01), Nara
patent: 5983383 (1999-11-01), Wolf
patent: 6005897 (1999-12-01), McCallister et al.
patent: 6023783 (2000-02-01), Divsalar et al.
patent: 6029264 (2000-02-01), Kobayashi et al.
patent: 6041432 (2000-03-01), Ikeda
patent: 6097764 (2000-08-01), McCallister et al.
patent: 6216251 (2001-04-01), McGinn
patent: 6266795 (2001-07-01), Wei
patent: 6317472 (2001-11-01), Choi et al.
patent: 6351832 (2002-02-01), Wei
patent: 6377610 (2002-04-01), Hagenauer et al.
patent: 6438717 (2002-08-01), Butler et al.
patent: 6473878 (2002-10-01), Wei
patent: 6625775 (2003-09-01), Kim
patent: 6671404 (2003-12-01), Kawatani et al.
patent: 6748034 (2004-06-01), Hattori et al.
patent: 6757862 (2004-06-01), Marianetti, II
patent: 6788654 (2004-09-01), Hashimoto et al.
patent: 6810502 (2004-10-01), Eidson et al.
patent: 6986098 (2006-01-01), Poeppelman et al.
patent: 7010051 (2006-03-01), Murayama et al.
patent: 7047474 (2006-05-01), Rhee et al.
patent: 7058873 (2006-06-01), Song et al.
patent: 7093179 (2006-08-01), Shea
patent: 7184486 (2007-02-01), Wu et al.
patent: 7191378 (2007-03-01), Eroz et al.
patent: 7203887 (2007-04-01), Eroz et al.
patent: 7257764 (2007-08-01), Suzuki et al.
patent: 7308061 (2007-12-01), Huang et al.
patent: 7310768 (2007-12-01), Eidson et al.
patent: 7346832 (2008-03-01), Richardson et al.
patent: 7415651 (2008-08-01), Argon
patent: 7434136 (2008-10-01), Ichihara et al.
patent: 7587657 (2009-09-01), Haratsch
patent: 7646829 (2010-01-01), Ashley et al.
patent: 7673213 (2010-03-01), Chugg et al.
patent: 7730384 (2010-06-01), Graef et al.
patent: 7779325 (2010-08-01), Song et al.
patent: 2004/0098659 (2004-05-01), Bjerke et al.
patent: 2005/0216819 (2005-09-01), Chugg et al.
patent: 2007/0047635 (2007-03-01), Stojanovic et al.
patent: 2008/0049825 (2008-02-01), Chen et al.
patent: 2008/0168330 (2008-07-01), Graef et al.
patent: WO 2006/016751 (2006-02-01), None
patent: WO 2006/091797 (2007-08-01), None
Seshadri et al., on post-decision symbol reliability generation, 1993, IEEE, p. 741-745.
Zhong, Hao et al., Joint Code-Encoder-Decoder Design for LDPC Coding System VLSI Implementation, Rensselaer Polytechnic Institute, printed Apr. 2007 from “www.ecse.rpi.edu”.
Zhong, Hao et al., Block-LDPC: A Practical LDPC Coding System Design Approach, IEEE, Jul. 2004, printed Apr. 2007 from “www.ecse.rpi.edu”.
Moon, Todd K., Error Correction Coding, 2005, pp. 640-649 John K. Wiley & Sons Inc., Hoboken, NJ.
Collins and Hizlan, “Determinate State Convolutional Codes” IEEE Transactions on Communications, Dec. 1993.
Eleftheriou, E. et al., “Low Density Parity Check Codes for Digital Subscriber Lines”, Proc ICC 2002, pp. 1752-1757.
Han and Ryan, “Pinning Techniques for Low-Floor Detection/Decoding of LDPC-Coded Partial Response Channels”, 5th International Symposium on Turbo Codes &Related Topics, 2008.
Mohsenin et al., “Split Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture”, pp. 1-6, printed from www.ece.ucdavis.edu on Jul. 9, 2007.
Vasic, B., “High-Rate Low-Density Parity-Check Codes Based on Anti-Pasch Affine Geometries,” Proc ICC 2002, pp. 1332-1336.
Vasic, B., “High-Rate Girth-Eight Codes on Rectangular Integer Lattices”, IEEE Trans. Communications, vol. 52, Aug. 2004, pp. 1248-1252.
Yeo et al., “VLSI Architecture for Iterative Decoders in Magnetic Storage Channels”, Mar. 2001, pp. 748-755, IEEE trans. Magnetics, vol. 37, No. 2.
Zhong et al., “Area-Efficient Min-Sum Decoder VLSI Architecture for High-Rate QC-LDPC Codes in Magnetic Recording”, pp. 1-15, Submitted 2006, not yet published.
Zhong et al., “Design of VLSI Implementation-Oriented LDPC Codes”, IEEE, pp. 670-673, 2003.
Zhong et al., “High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel with Low Error Floor”, ISCAS, IEEE pp. 3546-3549, May 2006.
Zhong et al., “Iterative MAX-LOG-MAP and LDPC Detector/Decoder Hardware Implementation for Magnetic Read Channel”, SRC TECHRON, pp. 1-4, Oct. 2005.
Zhong et al., “Joint Code-Encoder Design for LDPC Coding System VLSI Implementation”, ISCAS, IEEE pp. 389-392, May 2004.
Zhong et al., “Quasi Cyclic LDPC Codes for the Magnetic Recording Channel: Code Design and VSLI Implementation”, IEEE Transactions on Magnetics, v. 43, pp. 1118-1123, Mar. 2007.
Zhong, “VLSI Architecture of LDPC Based Signal Detection and Coding System for Magnetic Recording Channel”, Thesis, RPI, Troy, NY, pp. 1-95, May 2006.
Agere Systems Inc.
Chase Shelly A
Hamilton DeSanctis & Cha
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