Systems and methods for issuing address and data signals to...

Details Systems and methods for issuing address and data signals to... Systems and methods for issuing address and data signals to...

2008-09-03

2010-06-01

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Particular write circuit

C365S189050, C365S194000, C365S189120, C365S233100

Reexamination Certificate

active

07729182

ABSTRACT:
Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked loop may be used to compensate for additional delay experienced by the system clock relative to write clock and ensure synchronization of the clock signals. A write latch enable block may be used to develop a write latch enable signal for issuance along with a corresponding address signal. The write latch enable signal can be timed such that it arrives at an appropriate time to issue the data corresponding to the issued address.

REFERENCES:
patent: 5724553 (1998-03-01), Shigeeda
patent: 5737748 (1998-04-01), Shigeeda
patent: 6340897 (2002-01-01), Lytle et al.
patent: 6990076 (2006-01-01), McNamara et al.
patent: 7272054 (2007-09-01), Waldrop
Brian Johnson, Brent Keeth, Feng Lin and Hua Zheng; “Phase-Tolerant Latency Control for a Combination 512Mb 1.0Gb/s/pin GDDR3 and 2.5Gb/s/pin GDDR SDRAM”; 2007 IEEE International Solid-State Circuits Conference, Session 27, DRAM and eRAM; pp. 494-495 & 617.
Feng Lin, Roman A. Royer, Brian Johnson and Brent Keeth; “A Wide-Range Mixed-Mode DLL for a Combination 512 Mb 2.0 Gb/s/pin GDDR3 and 2.5 and 2.5 Gb/s/pin GDDR4 SDRAM”; IEEE Journal of Solid-State Circuits, vol. 43, No. 3, Mar. 2008; pp. 631-641.

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