Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-07-06
2010-10-05
Verbrugge, Kevin (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S152000, C711S163000, C711SE12029
Reexamination Certificate
active
07809890
ABSTRACT:
Systems and methods for increasing the yield of devices incorporating set-associative cache memories by selectively avoiding the use of cache entries that include defects. In one embodiment, a cache replacement manager determines in which of n possible entries data will be replaced. The cache replacement manager is configured to take into account whether each cache entry is defective when determining whether to select that entry as the destination entry for new data. The cache manager unit may implement a least-recently-used policy in selecting the cache entry in which the new data will be replaced. The cache replacement manager then treats any defective entries as if they hold the most recently used data, and thereby avoids selecting defective entries as the destination for new data. In one embodiment, the cache performs index translation before indexing into each set of cache entries in order to effectively redistribute defective entries among the indices.
REFERENCES:
patent: 4162541 (1979-07-01), Hartke
patent: 5070502 (1991-12-01), Supnik
patent: 5551004 (1996-08-01), McClure
patent: 5708789 (1998-01-01), McClure
patent: 5737753 (1998-04-01), Tsuchiya et al.
patent: 6418515 (2002-07-01), Kurosawa
patent: 7114035 (2006-09-01), Day et al.
patent: 2006/0179235 (2006-08-01), Bell et al.
patent: 59-94283 (1984-05-01), None
patent: 6-67980 (1994-03-01), None
patent: 8-50402 (1996-04-01), None
J Hennessy et. al, “Computer Architecture: A Quantitative Approach”, Third Edition, pp. 398-401, Pub. 2003.
David Culler et. al, “Parallell Computer Architecture: A Hardware/Software Approach”, pp. 394-397, Pub. 1999.
Nanya, T., Fault Tolerant Computer, p. 155, Copyright 1991.
The Asynchronous 24MB On-Chip Level-3 Cache for a Dual-Core Itanium Family Processor, Wuu et al., Feb. 9, 2005.
Kurosawa Yasuhiko
Takase Satoru
Cardwell Eric S
Kabushiki Kaisha Toshiba
Law Offices of Mark L. Berrier
Verbrugge Kevin
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