Systems and methods for improving memory reliability by...

Details Systems and methods for improving memory reliability by... Systems and methods for improving memory reliability by...

2006-11-09

2009-02-17

Yoha, Connie C (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S185230, C365S185220, C365S189090

Reexamination Certificate

active

07492649

ABSTRACT:
Systems and methods for reducing instability and writability problems arising from relative variations between a memory cell voltage (Vcell) and a logic voltage (Vdd) by inhibiting assertion of word line signals that enable accesses to the memory cells when the voltages are not within an acceptable operating range. One embodiment comprises a system having a critical condition detector configured to monitor the voltages and to determine whether the voltages are within an acceptable range. When the voltages are not within the acceptable range, the system inhibits assertion of the word lines to the memory cells. Memory accesses which fail because of the inhibited word line signals are retried by a memory controller when the critical conditions that caused the signals to be inhibited no longer exist.

REFERENCES:
patent: 6101126 (2000-08-01), Chung et al.
patent: 6144606 (2000-11-01), Pan
patent: 2008/0062747 (2008-03-01), Takase et al.

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