Systems and methods for improved memory scan testability

Details Systems and methods for improved memory scan testability Systems and methods for improved memory scan testability

2008-01-01

2008-01-01

Kerveros, James C. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

07315971

ABSTRACT:
A method and system for testing a device that includes both a digital and analog portion. The digital portion includes a plurality of latch devices, and the analog portion includes a plurality of memory cells and a plurality of selector devices. A selector input controls each of the plurality of selector devices, which is electrically coupled to a respective one of the memory cells, and is indirectly coupled to one of the plurality of latch devices. A load clock loads a pattern into the plurality of latch devices. A derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices with the assertion of the selector input. A system clock loads the derivative of the pattern into the plurality of latch devices.

REFERENCES:
patent: 6691269 (2004-02-01), Sunter
patent: 6959409 (2005-10-01), AbdEl-Wahid
patent: 2005/0080581 (2005-04-01), Zimmerman et al.

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