Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-11-28
2006-11-28
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07143389
ABSTRACT:
Systems and methods associated with generating node level bypass capacitor models are disclosed. One embodiment of a system may comprise a plurality of bypass capacitor circuit models associated with respective bypass capacitors and a node level model generator. The node level model generator may associate bypass capacitor information for a plurality of bypass capacitors from a data base associated with a multi-layer structure design with respective bypass capacitor circuit models to provide a node level capacitor model for the plurality of bypass capacitors.
REFERENCES:
patent: 5610833 (1997-03-01), Chang et al.
patent: 5691910 (1997-11-01), Thodiyil
patent: 5838947 (1998-11-01), Sarin
patent: 5889685 (1999-03-01), Ramachandran
patent: 6345379 (2002-02-01), Khouja et al.
patent: 6449578 (2002-09-01), McBride
patent: 6532439 (2003-03-01), Anderson et al.
patent: 6571184 (2003-05-01), Anderson et al.
patent: 6584598 (2003-06-01), Rao et al.
patent: 6675118 (2004-01-01), Wanek et al.
patent: 2003/0212973 (2003-11-01), Lin et al.
patent: 2004/0078767 (2004-04-01), Burks et al.
Frank Mark D.
Nelson Jerimy
Wang Yong
LandOfFree
Systems and methods for generating node level bypass... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Systems and methods for generating node level bypass..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods for generating node level bypass... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3687488