Systems and methods for generating hardware description code

Details Systems and methods for generating hardware description code Systems and methods for generating hardware description code

2000-11-28

2003-03-25

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C707S793000, C707S793000, C707S793000, C707S793000, C709S203000, C717S106000, C717S114000, C717S140000

Reexamination Certificate

active

06539520

ABSTRACT:

REFERENCE TO COMPUTER PROGRAM LISTING APPENDICES
Two (2) duplicate compact discs, each containing two files named “App_a.txt” and “App_b.txt”, corresponding respectively to Appendix A and Appendix B, are incorporated herein by reference.
The present invention relates generally to generating hardware description language code, and more particularly to systems and methods for generating boundary scan configuration files and VERILOG netlists.
BACKGROUND OF THE INVENTION
To reduce the cost of device component and system testing, integrated circuits (ICs) and printed circuit boards (PCBs) often have built-in-self-test (BIST) features incorporated into the components. To standardize the test methodology and port architecture, the Joint Test Access Group (JTAG) created the Institute for Electrical and Electronic Engineers (IEEE) standard 1149.1, also known as IEEE Standard Test Access Port and Boundary Scan Architecture. IEEE standard 1149.1 defines a four to five wire serial interface, an instruction set, and a test protocol. The test port of an 1149.1 standard device allows for serial loading of test instructions and data into the device, and for the test results to be serially read out.
JTAG Compliant Device Architecture
FIG. 1
illustrates an IEEE 1149.1 compatible device
10
. A JTAG compatible device has a four pin test port (TCK=Test Clock
20
, TMS=Test Mode Select
30
, TDI=Test Data In
40
, and TDO=Test Data Out
50
), an optional 5
th
reset pin (TRST=Test Reset
60
), a Test Access Port (TAP) Controller
70
, an Instruction Register (IR)
80
, a Bypass register (BPR)
90
, a Boundary Scan Register (BSR)
100
, and an optional user Data Register (DR)
110
. Each input and output pin of a 1149.1 compatible device has a Boundary Scan Cell (BSC)
120
and
122
, which contains a set of control registers and gates (not shown). The boundary scan register or BSR
100
is made up of serially connected BSCs
120
and
122
as illustrated in FIG.
1
. Serially connected BSCs
120
and
122
are also called the scan path. The boundary scan chain is the path from TDI
40
, through the BSR
100
, to TDO
50
.
The TAP controller
70
is a state machine that, in conjunction with the IR
80
, controls operations associated with the BSR
100
. The TAP controller
70
is clocked by TCK
20
, and its state is controlled by TMS
30
. TDI
40
and TDO
50
receive the data input and output signals for the boundary scan chain. Working in conjunction with the TAP controller
70
, the IR
80
is loaded with instructions that determine the particular test to be performed.
There are three required test instructions defined by IEEE Std 1149.1, BYPASS, SAMPLE/PRELOAD, and EXTEST. The BYPASS instruction keeps the IC in a functional mode, and enables serial data to pass through the IC from TDI
40
through the BPR
90
to TDO
50
without affecting the operation of the rest of the device. The SAMPLE/PRELOAD instruction keeps the IC in its functional mode, and selects BSR
100
to be connected between TDI
40
and TDO
50
. Executing SAMPLE/PRELOAD instruction allows the BSR
100
to be accessed to sample the data entering and leaving the IC or to preload test data into the BSR
100
. The EXTEST instruction places the IC into a test mode, and selects the BSR
100
to be connected between TDI
40
and TDO
50
. Executing EXTEST loads the BSCs
122
associated with output pins
130
with the test patterns to be input into downstream devices, and prepares the input boundary cells
120
to capture the input data.
VERILOG Netlist and Boundary Scan Description Language Files
A hardware description language (HDL) is a code for describing a circuit. A primary use of HDLs is the simulation of designs before the designer must commit to fabrication. The two most popular HDLs are VHSIC Hardware Description Language (VHDL) and VERILOG. VHDL was developed by the U.S. Department of Defense and is an open standard. VERILOG, also called Open VERILOG International (OVI), is an industry standard developed by a private entity, and is now an open standard referred to as IEEE Standard 1364. A file written in VERILOG code that describes a JTAG compliant device is called a VERILOG netlist. VHDL is an HDL defined by IEEE standard 1076.1. Boundary Scan Description Language (BSDL) is a subset of VHDL, and provides a standard machine- and human-readable data format for describing how an IEEE Std 1149.1 boundary-scan architecture is implemented and operates in a device.
Commercial products exist that generate the boundary scan description language (BSDL) files and VERILOG netlists. To generate a BSDL file, such products generally require input files with many parameters and must be composed using exact syntax. For instance, a BSDL description for a device consists of several elements. These elements include entity descriptions, a generic parameter, a logical port description, use statement(s), a component conformance statement, pin mapping(s), a scan port identification, an instruction register description, an optional register description, a register access description, and a boundary register description. Some products require an input file containing a register transfer language (RTL) representation of the device, such as a VERILOG or VHDL description. Other products require an input file with device parameters specified by a manufacturer defined syntax. To generate the files in the proper format requires learning the various programming languages or manufacturer defined syntax. When the files are created, even small errors in syntax can result in time-consuming debugging of the input files. Consequently, generating the input files that describe the boundary scan architecture is time-consuming and requires a skilled programmer. Thus, the current systems and methods of generating VERILOG netlists and BSC files are labor intensive, prone to inaccuracies, and slow. Systems and methods of improving the speed, accuracy, and simplicity of generating HDL files are needed.
SUMMARY OF THE INVENTION
The present invention includes systems, methods, scripts, and signals useful for generating hardware description language (HDL) files that describe circuits. To generate an HDL file, a user may access a hardware description code generation host, typically via the Internet, and upload information about the circuit. The hardware description code generation host may in turn generate an HDL file from the uploaded information, referred to as the input parameters, which the user uploads to the host. The hardware description code generation host utilizes scripts, which are generally software programs, to generate the files from the input parameters. The input parameters contain information about the ports of the device, which are utilized in generating the files. Information about the format for entering the input parameters may be displayed to the user on the same webpage as the input form, or through a separate webpage easily accessible by clicking on hyperlinks to other webpages. Moreover, the user may customize the input format to suit his particular needs. After the hardware description language files are generated, the user may save or download the files from the host.
The present invention has several advantages over the prior art. First, the present invention eliminates the labor intensive processes of learning the HDL syntax and debugging the HDL files to correct syntax errors. Instead of having to learn an HDL-like VERILOG or BSDL to generate HDL files, the user will input simple port descriptions and the script will generate the files. Second, the details of the input format for entering the input parameters may be displayed on the input form, which will eliminate the need to memorize the input format, or the cumbersome process of referring to a manual to learn formatting details. The present invention even allows a user to customize the input format to his own needs. Third, since VERILOG netlists and BSDL files differ significantly, a user typically generates each separately. The present invention all

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