Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-11-27
2007-11-27
Song, Jasmine (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S137000, C711S140000, C711S204000, C712S216000
Reexamination Certificate
active
10988284
ABSTRACT:
Methods for executing load instructions are disclosed. In one method, a load instruction and corresponding thread information are received. Address information of the load instruction is used to generate an address of the needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load and/or store instruction specifying the same address. If such a previous load/store instruction is found, the thread information is used to determine if the previous load/store instruction is from the same thread. If the previous load/store instruction is from the same thread, the cache hit signal is ignored, and the load instruction is stored in the queue. A load/store unit is also described.
REFERENCES:
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patent: 6578065 (2003-06-01), Aglietti et al.
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Barrick Brian David
Fernsler Kimberly Marie
Hicks Dwain A.
Osanai Takeki
Ray David Scott
Carr LLP
Rifai D'Ann N.
Song Jasmine
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