Systems and methods for ensuring correct connectivity...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07039892

ABSTRACT:
Systems, methods and software products ensure correct connectivity between circuit designs. A list of connections of the circuit designs is generated. One or more mapping files are generated from the list to correlate connections between the circuit designs. The mapping file is regenerated in response to modification of at least one of the circuit designs. Optionally, at least one schematic associated with at least one of the circuit designs is regenerated using information in the regenerated mapping file

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Nakamura et al, “Lores—Logic Reorganization System”, Proceedings of the Fifteenth Design Automation Conference, Las Vegas, NV, 1978, pp. 250-260.

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