Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-18
2004-06-15
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S506000, C257S508000, C257S510000, C257S521000
Reexamination Certificate
active
06750516
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductors. More specifically, the invention relates to systems and methods pertaining to semiconductors that incorporate one or more electrically isolated portions.
2. Description of the Related Art
Semiconductor wafers oftentimes are arranged in an overlying relationship with each other and are bonded together to form a wafer stack. In order to facilitate communication of processing of one wafer of such a wafer stack with processing of another wafer, various interconnecting structures may be used. For example, wires can be used to interconnect components of the various wafers so that the components can electrically communicate with each other. In other wafer stacks, conductor vias can be used. A representative example of such a via is depicted in FIG.
1
.
As shown in
FIG. 1
, wafer
100
includes a via structure
102
that is formed through the material of the wafer. Via structure
102
includes an insulator ring
104
that is formed about a conductor
106
. Via structure
102
permits the propagation of low voltage signals from one side of wafer
100
to the other side. More specifically, such a signal can be propagated from one side of the wafer to the other through conductor
106
. Unfortunately, via structure
102
tends to breakdown or short when relatively large potential differences exist between the conductor
106
and the substrate
108
. Thus, it can be appreciated that there is a need for improved systems and methods that address these and/or other shortcomings of the prior art.
SUMMARY OF THE INVENTION
Briefly described, the present invention relates to semiconductors that incorporate one or more electrically isolated portions. In this regard, embodiments of the invention may be construed as providing methods for electrically isolating portions of wafers. A representative method includes the steps of: providing a first wafer; forming a first conductor at least partially through the first wafer; disposing first dielectric material between the first conductor and material of the first wafer; and at least partially surrounding the first conductor and the first dielectric material with second dielectric material. Preferably, the second dielectric material is spaced from the first dielectric material so that a first portion of the material of the first wafer is arranged between the first dielectric material and the second dielectric material and a second portion of the material of the first wafer is arranged outside an outer periphery of the second dielectric material.
Embodiments of the invention also may be construed as providing systems for electrically isolating portions of wafers. In this regard, a representative embodiment includes a first wafer and a first conductor formed at least partially through the first wafer. A first conductor insulating layer is formed at least partially through the first wafer. The first conductor insulating layer engages the first conductor and is disposed between the first conductor and material of the first wafer. A first outer insulating layer also is provided that is formed at least partially through the first wafer. The first outer insulating layer is spaced from the first conductor insulating layer. Both the first conductor insulating layer and the first outer insulating layer are formed of dielectric material.
Other systems, methods, features, and advantages of the present invention will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present invention, and be protected by the accompanying claims.
REFERENCES:
patent: 4688069 (1987-08-01), Joy et al.
patent: 4733287 (1988-03-01), Bower
patent: 4939567 (1990-07-01), Kenney
patent: 4949151 (1990-08-01), Horiuchi et al.
patent: 5644157 (1997-07-01), Iida et al.
patent: 5760452 (1998-06-01), Terada
patent: 6051868 (2000-04-01), Watanabe et al.
patent: 6472723 (2002-10-01), Jarstad et al.
patent: 6515334 (2003-02-01), Yamazaki et al.
Hewlett--Packard Development Company, L.P.
Niebling John F.
Pompey Ron
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