Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-01
2006-08-01
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07086019
ABSTRACT:
Systems, methods and software products determine activity factors of a circuit design. An activity factor is assigned to one or more node types. One or more signal nets from a netlist of the circuit design are read. The signal nets are processed to associate one of the node types with each of the signal nets. An activity factor is determined for each of the signal nets based upon node type.
REFERENCES:
patent: 5249133 (1993-09-01), Batra
patent: 5301318 (1994-04-01), Mittal
patent: 5668732 (1997-09-01), Khouja et al.
patent: 5673420 (1997-09-01), Reyes et al.
patent: 5682320 (1997-10-01), Khouja et al.
patent: 5696694 (1997-12-01), Khouja et al.
patent: 5831869 (1998-11-01), Ellis et al.
patent: 5838579 (1998-11-01), Olson et al.
patent: 5903476 (1999-05-01), Mauskar et al.
patent: 5946218 (1999-08-01), Taylor et al.
patent: 5949691 (1999-09-01), Kurosaka et al.
patent: 6028991 (2000-02-01), Akashi
patent: 6075932 (2000-06-01), Khouja et al.
patent: 6185722 (2001-02-01), Darden et al.
patent: 6230299 (2001-05-01), McSherry et al.
patent: 6272671 (2001-08-01), Fakhry
patent: 6308304 (2001-10-01), Devgan et al.
patent: 6330703 (2001-12-01), Saito et al.
patent: 6345379 (2002-02-01), Khouja et al.
patent: 6363516 (2002-03-01), Cano et al.
patent: 6378123 (2002-04-01), Dupenloup
patent: 6480987 (2002-11-01), McBride
patent: 6490717 (2002-12-01), Pederson et al.
patent: 6493864 (2002-12-01), Liu
patent: 6523149 (2003-02-01), Mehrotra et al.
patent: 6529861 (2003-03-01), Patra et al.
patent: 6531923 (2003-03-01), Burns
patent: 6587999 (2003-07-01), Chen et al.
patent: 6598211 (2003-07-01), Zachariah et al.
patent: 6751782 (2004-06-01), Levin et al.
patent: 6772404 (2004-08-01), Tanaka
patent: 6801884 (2004-10-01), Ferreri et al.
patent: 6807520 (2004-10-01), Zhou et al.
patent: 6836877 (2004-12-01), Dupenloup
patent: 6931613 (2005-08-01), Kauth et al.
patent: 2002/0002701 (2002-01-01), Usami et al.
patent: 2002/0010901 (2002-01-01), Otaguro
patent: 2002/0023255 (2002-02-01), Karniewicz
patent: 2002/0144219 (2002-10-01), Zachariah et al.
patent: 2003/0051222 (2003-03-01), Williams et al.
patent: 2003/0200519 (2003-10-01), Argyres
patent: 2003/0208721 (2003-11-01), Regnier
patent: 2003/0221173 (2003-11-01), Fisher
patent: 2003/0237067 (2003-12-01), Mielke et al.
patent: 2004/0044972 (2004-03-01), Rohrbaugh et al.
patent: 2004/0078767 (2004-04-01), Burks et al.
patent: 2004/0199880 (2004-10-01), Kresh et al.
patent: 07334532 (1995-12-01), None
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,682, Entitled: Method And Program Product For Determining Nets Requiring Detailed Electromigration And Self Heating Analysis In A Digital Integrated Circuit; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,698, Entitled: Method And Program Product For Performing Self-Heating Analysis In A Digital Integrated Circuit Through a Single Cycle Transient Simulation; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,376, Entitled: Method And Program For Visual Display and One-Click Repair Of Electromigration And Self Heating Design-Rule Violations In A Digital Integrated Circuit Layout Database; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,501, Entitled: Method And Program Product For Performing Electromigration Analysis In A Digital Integrated Circuit By Converting A Netlist To A DC Model And Performing DC Analysis Of The DC Model; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,526, Entitled: Method And Program Product For Performing A Worst Case Electromigration And Self Heating Analysis In A Digital Integrated Circuit With Worse-Case Superposition Of Partial Currents; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,692, Entitled: Method And Program Product For Performing Electromigration Analysis In A Digital Integrated Circuit Through A Single Cycle Transient Simulation; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,508, Entitled: Method And Program Product For Performing Self-Heating Analysis In A Digital Integrated Circuit Layout Database by Substituting Resistive Models For Active Devices; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655516US; Entitled: Method And Program Prodcut For Determining Worst Case Currents In A Digital Integrated Circuit Through Worst-Case Superposition Of Partial Currents; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655564US; Entitled: Systems And Methods For Re-Using Circuit Design Analysis Results; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655581US; Entitled: System And Method For Determining Detail Of Analysis In A Circuit Design; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655595US; Entitled: Systems And Methods That Identify Equivalent Instantiation-Specific Configuration Information For Analysis Tools; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H. & Stevens, Scott Alan; U.S. Patent Application filed under EV210655520US; Entitled: System And Method To Limit Analyzed Current Flow In A Circuit Design; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655533US; Entitled: System And Method For Processing Configuration Information; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655555US; Entitled: System And Method For Balancing Run-Time And Result Accuracy In A Circuit Design Analysis Tool; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655578US; Entitled: System And Method For Indicating Logic State Combinations Used During Circuit Design Analysis; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655547US; Entitled: System And Method For Determining Control Signal Combinations For Use During Simulation Of A Stage Of A Circuit Design; Filed Jan. 30, 2004.
Keller S. Brandon
Robbert George Harold
Rogers Gregory Dennis
Hewlett--Packard Development Company, L.P.
Levin Naum
Siek Vuthe
LandOfFree
Systems and methods for determining activity factors of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Systems and methods for determining activity factors of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods for determining activity factors of a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3706431