Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
1999-07-21
2001-01-30
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S158000, C375S375000
Reexamination Certificate
active
06181178
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to clocking systems and methods for integrated circuits and more particularly to duty cycle correction systems and methods for clock signals.
BACKGROUND OF THE INVENTION
As the operating speed of integrated circuit devices continues to increase, it may become increasingly important to provide duty cycle correction for clock sources. In particular, when a clock signal is received from internal or external of the integrated circuit and has a duty cycle that is different from 50%, it may become important to correct the duty cycle to 50%. Duty cycle correction systems and methods for clock signals are described in U.S. Pat. Nos. 4,527,075 to Zbinden, entitled Clock Source with Automatic Duty Cycle correction; 5,491,440 to Uehara et al., entitled Automatic Clock Duty Cycle Adjusting Circuit; 5,572,158 to Lee et al., entitled Amplifier with Active Duty Cycle correction; and 5,757,218 to Blum, entitled Clock Signal Duty Cycle correction Circuit and Method. Duty cycle correction systems and methods may be applied to integrated circuits including logic, microprocessor and memory integrated circuits and integrated circuits that combine two or more of these or other functions.
One type of memory integrated circuit to which duty cycle correction systems and methods may be applied employs the Rambus technology marketed by Rambus, Inc. of Mountain View, Calif. The Rambus technology is described in U.S. Pat. Nos. 5,473,575 to Farmwald et al.; 5,578,940 to Dillion et al.; 5,606,717 to Farmwald et al. and 5,663,661 to Dillion et al. A device embodying the Rambus technology is an example of a packet type integrated circuit memory device, because each integrated circuit receives data and addresses in packet units in a normal mode of operation. The packet is received by the Rambus device which generates internal control signals, internal data signals and internal address signals to carry out the corresponding operation of the packet. For example, the packet may include data, address and control signals for a write operation.
FIG. 1
is a block diagram of an input receiver for an integrated circuit such as a Rambus memory device. As shown in
FIG. 1
, an input receiver
101
receives a clock signal PCLK, data DB and a reference voltage Vref. The input receiver
101
converts the voltage level of the data DB and outputs the result as complementary data signals DO and {overscore (DO)}. For a Rambus device, the data DB may have Transistor-Tranisistor logic (TTL) levels and the data output DO, {overscore (DO)} may have Complementary Metal Oxide Semiconductor (CMOS) logic levels. Thus, the input receiver
101
amplifies the difference between the input data DB and the reference voltage Vref to convert the input data DB from To TTL levels to CMOS levels, and outputs the data DO and {overscore (DO)} at CMOS levels. The clock signal PCLK preferably is a duty cycle-corrected clock signal.
Notwithstanding the provision of a duty cycle-corrected clock signal, it still may be difficult to operate integrated circuits at high speeds such as several hundred megaHertz. It may be particularly difficult to operate integrated circuits at high speeds when data is processed at both the rising and the falling edges of a clock signal. In particular, as shown in
FIG. 2A
, when duty cycles of the data DB and the clock signal CLK are both 50%, the sum of the setup time ts and the hold time th of the data DB may equal 50%. Thus, a maximum margin may be allowed for setup time and hold time. However, as shown in
FIG. 2B
, if the duty cycles of the data DB and the clock signal CLK are within a range of 40%, the duty cycle of the clock signal CLK may be restored to 50% but the data DB is input to the input receiver
101
as is. Thus, the setup ts and the hold time th may decrease compared to FIG.
2
A. Conversely, when the duty cycles of the data DB and the clock signal CLK are within an allowable range of 60%, the setup time ts and the hold time th may increase compared to data having a duty cycle of 50%. The above described increases and decreases may reduce the operating margins of the integrated circuit which may thereby impact the speed and/or performance thereof.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved systems and methods for correcting duty cycle deviations in integrated circuits.
It is another object of the present invention to provide improved duty cycle correction in integrated circuits that already include clock duty cycle correction.
These and other objects are provided, according to the present invention, by generating a duty cycle-corrected clock signal from a clock signal and by generating a reference signal that is based upon a duty cycle deviation between the duty cycle-corrected clock signal and the clock signal. Input data is compared to the reference signal in response to the duty cycle-corrected clock signal, to thereby generate duty cycle-corrected output data. Thus, the clock signal and the input data are both duty cycle-corrected to thereby allow an increase in the operating margins of the integrated circuit. The performance and/or speed of the integrated circuit thereby may be increased.
In one embodiment, at least one duty cycle control signal is generated based upon a duty cycle deviation between the duty cycle-corrected clock signal and the clock signal. A second reference voltage is generated from a first reference voltage and from the at least one duty cycle control signal. The input data is then compared to the second reference voltage in response to the duty cycle-corrected clock signal, to thereby generate the duty cycle-corrected output data.
In a preferred embodiment, the at least one duty cycle control signal comprises at least two duty cycle control signals that are proportional to the duty cycle deviation between the duty cycle-corrected clock signal and the clock signal. The first reference voltage and the at least two duty cycle control signals are summed in order to generate the second reference voltage. More specifically, a first and a second duty cycle control signal are provided. The second duty cycle control signal is inverted. The first reference voltage, the first duty cycle control signal and the inverted second duty cycle control signal are summed to produce a summed signal. The summed signal is inverted to produce the second reference voltage.
Thus, the second reference voltage preferably is less than the first reference voltage when the duty cycle of the clock signal is less than a predetermined duty cycle, for example a 50% duty cycle, and is greater than the first reference voltage when the duty cycle of the clock signal is greater than the predetermined duty cycle. Alternatively, when first and second duty cycle control signals are provided, the first duty cycle control signal preferably is greater than the second duty cycle control signal when the duty cycle of the clock signal exceeds a predetermined duty cycle such as a 50% duty cycle, and the first duty cycle control signal is less than the second duty cycle control signal when the duty cycle of the clock signal is less than the predetermined duty cycle.
In an integrated circuit implementation, a plurality of pads may be provided. A delay locked loop is provided that is responsive to a clock signal that is received from at least a first one of the plurality of pads, to generate the duty cycle-corrected clock signal from the clock signal and to generate the at least one duty cycle control signal that is based upon the duty cycle deviation between the duty cycle-corrected clock signal and the clock signal. A first reference voltage generator generates the first reference voltage. A second reference voltage generator generates the second reference voltage from the first reference voltage and from the at least one duty cycle control signal. A data receiver compares input data that is received from at least a second one of the plurality of pads to the second reference voltage, in response to the duty cycle-corrected clock
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Wells Kenneth B.
LandOfFree
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