Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2008-03-24
2011-12-27
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711SE12014, C711SE12078
Reexamination Certificate
active
08086806
ABSTRACT:
One embodiment of the present invention sets forth a technique for efficiently and flexibly performing coalesced memory accesses for a thread group. For each read application request that services a thread group, the core interface generates one pending request table (PRT) entry and one or more memory access requests. The core interface determines the number of memory access requests and the size of each memory access request based on the spread of the memory access addresses in the application request. Each memory access request specifies the particular threads that the memory access request services. The PRT entry tracks the number of pending memory access requests. As the memory interface completes each memory access request, the core interface uses information in the memory access request and the corresponding PRT entry to route the returned data. When all the memory access requests associated with a particular PRT entry are complete, the core interface satisfies the corresponding application request and frees the PRT entry.
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Hirota Gentaro
Mandal Tanmoy
Nickolls John R.
Nyland Lars
Bragdon Reginald
NVIDIA Corporation
Patterson & Sheridan LLP
Ruiz Aracelis
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