Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-10-03
2006-10-03
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S127000, C711S143000, C710S053000
Reexamination Certificate
active
07117310
ABSTRACT:
Systems and methods for maintaining cache coherency between a first controller and a redundant peer controller while reducing communication overhead processing involved in the coherency message exchange. Header or meta-data information is accumulated in a buffer in a first controller along with updated cache data (if any) and forwarded to the peer controller. The accumulating information may be double buffered so that a buffer is filling as a previously filled buffer is transmitting to the peer controller. The peer controller processes the received information to update its mirror cache to maintain coherency with the first controller's cache memory with respect to dirty data. The method and systems avoid the need to update cache coherency in response to every flush operation performed within the first controller to thereby improve overall system performance.
REFERENCES:
patent: 5559952 (1996-09-01), Fujimoto
patent: 6247099 (2001-06-01), Skazinski et al.
patent: 6912669 (2005-06-01), Hauck et al.
Biswas Chayan
Chatterjee Paresh
Mishra Ragendra
Thangaraj Senthil
Duft Bornsen & Fishman LLP
LSI Logic Corporation
Moazzami Nasser
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