Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-02-10
2003-11-18
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S001000, C710S004000, C710S007000, C710S033000, C710S036000, C710S052000, C710S107000, C710S112000, C710S113000, C710S310000, C710S241000, C710S242000
Reexamination Certificate
active
06651128
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to electronic systems which transfer data and, more particularly, to electronic systems used to convey both asynchronous and isochronous data.
2. Description of the Related Art
A typical modem personal computer system includes a central processing unit (CPU) coupled to a main memory and a local bus (e.g., a peripheral component interconnect or PCI bus) through bridge circuitry. The bridge circuitry functions as an interface between the CPU and the main memory, and may include a memory controller. The bridge circuitry also functions as an interface between the CPU and various peripheral and input/output (I/O) devices coupled to the local bus.
Most data exchanges within a personal computer system occur intermittently rather than in a steady stream. Such “asynchronous” data transmissions include CPU accesses to main memory and data transmissions between a hard drive coupled to the local bus and main memory. Asynchronous data transmissions are separated by idle periods of arbitrary length. On the other hand, multimedia data such as video and audio data must be presented in a continuous manner, thus the transmission of multimedia data is time dependent or “isochronous” . Such isochronous data transmissions tend to occur at substantially regular time intervals and require a certain minimum data rate to support continuous presentation (i.e., “isochrony”). Modern personal computer systems support both asynchronous and isochronous data transfers.
Both asynchronous and isochronous data are conveyed along substantially the same transmission paths within the computer system, and compete for the same transmission resources (e.g., buses). As mentioned above, asynchronous data transmissions include CPU accesses to main memory. Performance of the personal computer system is thus highest when asynchronous data is conveyed as quickly as possible through the system.
It is noted that in most cases, the data bandwidth of isochronous data is much less than the data bandwidths of transmission resources such as buses used to convey both asynchronous and isochronous data. Also, there are typically sufficient idle times between asynchronous data transfers to support isochronous data transfers.
It would thus be desirable to have a system for arbitrating between asynchronous and isochronous data for access to transmission resources which maximizes a transfer rate of asynchronous data. When such an arbitration system is incorporated within a personal computer, the performance of the personal computer system is maximized.
SUMMARY OF THE INVENTION
Several different systems and methods are described involving arbitration between asynchronous and isochronous data for access to a data transport resource (e.g., a bus or a memory controller). A first embodiment of a system (e.g., a computer system or a communication system) includes an arbiter coupled to the data transport resource, an asynchronous queue for storing asynchronous data, and an isochronous queue for storing isochronous data. The isochronous queue has a data level range divided into multiple portions. The arbiter arbitrates between the asynchronous queue and the isochronous queue for access to the data transport resource dependent upon the portion of the data level range in which a level of data resides within the isochronous queue.
For example, the isochronous queue may include multiple memory locations operated in a first-in-first-out (FIFO) manner. In this case, the number of memory locations within the isochronous queue defines the data level range of the isochronous queue. The isochronous queue may also include a write pointer which indicates the next available memory location for storing isochronous data, and a read pointer which indicates the next memory location containing unread isochronous data. The level of data within the isochronous queue may be the number of memory locations between the write pointer and the read pointer.
The arbiter may include a set of arbitration rules, wherein each arbitration rule states conditions used to determine whether data is provided from the isochronous queue or the asynchronous queue. The arbiter may arbitrate between the asynchronous queue and the isochronous queue for access to the data transport resource by: (i) selecting an arbitration rule from the set of arbitration rules dependent upon the portion of the data level range in which the level of data resides within the isochronous queue, and (ii) applying the rule.
The data level range of the isochronous queue may extend between a maximum value and a minimum value. An upper portion of the data level range may include the maximum value, and a lower portion of the data level range may include the minimum value. Other portions of the data level range may exist between the upper and lower portions.
When the system is a computer system, performance of the computer system is highest when asynchronous data is conveyed as quickly as possible through the computer system. The level of data within the isochronous queue is relatively low when the level of data resides in the lower portion of the data level range. The arbiter may select a first rule from the set of arbitration rules when the level of data within the isochronous queue is relatively low. In order to convey asynchronous data as quickly as possible through the computer system, the asynchronous queue may receive priority over the isochronous queue for access to the data transport resource under the first rule.
The level of data within the isochronous queue is relatively high when the level of data resides in the upper portion of the data level range. The arbiter may select a second rule from the set of arbitration rules when the level of data within the isochronous queue is relatively high. The isochronous queue may receive increased consideration for access to the data transport resource under the second rule than under the first rule in order to avoid an overflow condition within the isochronous queue.
The arbiter may receive a signal indicating a need for isochronous data, and may allow the isochronous queue access to the data transport resource in response to the signal in order to maintain isochrony.
The asynchronous queue may receive asynchronous data and provide the asynchronous data in an order received. The asynchronous data may include memory read and write commands and associated data values. The isochronous queue may receive isochronous data and provide the isochronous data in an order received. The isochronous data may include video data or audio data.
A first method for providing data, which may be embodied within the first system described above, includes dividing the data level range of the isochronous queue into multiple portions. A single one of a set of arbitration rules is associated with each portion of the data level range. As described above, each arbitration rule states conditions used to determine whether data is provided from the isochronous queue or an asynchronous queue. A different arbitration rule may be associated with each portion of the data level range. Alternately, a given arbitration rules may be associated with more than one of the portions of the data level range. The level of data within the isochronous queue is determined, and a target portion of the data level range in which the level of data resides is determined. The arbitration rule associated with the target portion of the data level range is applied in order to provide data from either the isochronous queue or the asynchronous queue.
A second embodiment of a system (e.g., a computer system or a communication system) includes an arbiter coupled to the data transport resource, multiple asynchronous queues for storing asynchronous data, and multiple isochronous queues for storing isochronous data. Each isochronous queue includes a data level range divided into multiple portions as described above. The arbiter arbitrates between the asynchronous queues and the isochronous queues for access to the data transport resource dependent u
Advanced Micro Devices , Inc.
Farooq Mohammad O.
Gaffin Jeffrey
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
LandOfFree
Systems and methods for arbitrating between asynchronous and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Systems and methods for arbitrating between asynchronous and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods for arbitrating between asynchronous and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3147431