Systems and methods for actively-peaked current-mode logic

Details Systems and methods for actively-peaked current-mode logic Systems and methods for actively-peaked current-mode logic

2007-10-30

2007-10-30

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar transistor

C326S115000, C326S126000

Reexamination Certificate

active

11691859

ABSTRACT:
A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND gates, OR gates, flip-flops, and latches. The current steering cells with actively-peaked loads can provide benefits such as reduced power consumption, smaller area, and higher speed performance over conventional devices. This performance boost is preferably achieved using NMOS followers with resistively degenerated gates to create frequency peaked transfer function of current-mode logic cells. These logic cells with actively-peaked loads can advantageously be used in circuits in which relatively good power area and performance are desired for state machine logic, parallel to serial conversions, serial to parallel conversions, and the like.

REFERENCES:
patent: 6788103 (2004-09-01), Feldman et al.
patent: 2004/0227573 (2004-11-01), Soda

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