Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-12-29
2010-11-16
Choe, Yong (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S103000, C711SE12093, C711SE12008, C710S005000, C713S193000
Reexamination Certificate
active
07836269
ABSTRACT:
Systems and methods that facilitate processing data and securing data written to or read from memory. A processor can include a host memory interface that monitors all bus traffic between a host processor and memory. The host memory interface can analyze commands generated by the host processor and determine the validity of the commands. Valid commands can proceed for further analysis; invalid commands can be aborted, for example, with the host memory interface and memory each set to an idle state. The host memory interface can analyze authentication information obtained via an authentication component, and information regarding memory partition rights, to determine whether a command partition violation exists as to the command. If a violation exists, the host memory interface can prevent the improper command from executing in the memory, and can cause a different operation to occur thereby allowing the memory to be placed in a known state.
REFERENCES:
patent: 2003/0099231 (2003-05-01), Betts et al.
patent: 2007/0245036 (2007-10-01), Fekih-Romdhane
patent: 2007/0260836 (2007-11-01), Rudelic
patent: 2008/0126813 (2008-05-01), Kawakami
Lee Hyun Soo
Natarajan Venkat
Obereiner Willy
Tom Joe Yuen
Werner Jeremy Isaac Nathaniel
Choe Yong
Spansion LLC
Turocy & Watson LLP
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