Systems and methods for a memory and/or selection element...

Details Systems and methods for a memory and/or selection element... Systems and methods for a memory and/or selection element...

2007-04-03

2007-04-03

Ho, Tu-Tu (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S594000, C257SE27091, C257SE27095

Reexamination Certificate

active

10985172

ABSTRACT:
The subject invention provides systems and methodologies for fabrication of memory and/or selection (e.g., diodes) elements in a recession in a semiconductor layer. In particular, a trench of varying width is created in the semiconductor layer by employing various etching techniques. A metal film can be deposited in the trench according to a desired deposition thickness in order to seam close a narrow portion of the trench while form a dimple in a wide portion of the trench. The trench, after metal film deposition, exhibits a depression in wider trench portions relative to narrow trench portions. The depression can be utilized by placing one or more memory or selection layers in the depression, and a via can be formed over a portion of the trench to form an interconnect.

REFERENCES:
patent: 2002/0102839 (2002-08-01), Gonzalez et al.
patent: 2005/0184327 (2005-08-01), Ozawa

Affiliated with

Also associated with

Rating

Systems and methods for a memory and/or selection element... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Systems and methods for a memory and/or selection element..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods for a memory and/or selection element... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3734162