Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2006-09-12
2006-09-12
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
Reexamination Certificate
active
07107393
ABSTRACT:
An asynchronous FIFO buffer communicates data between an input clock domain and a relatively slow output clock domain. The input clock frequency is not an even multiple of the output clock frequency, so the data transfer is asynchronous. The FIFO buffer includes a collection of input registers, a shift register, and some clock-comparison and write logic that controls the flow of data into, out of, and between these registers. The input data is loaded into the input registers in synchronization with the input clock. The clock-comparison and write logic compares the input and output clock signals and moves the data from the input registers to the shift register at an address value that may vary based on the result of the comparison of the input and output clock signals, skipping write cycles as necessary to avoid shifting data into the shift register faster than the data is shifted out.
REFERENCES:
patent: 4672609 (1987-06-01), Humphrey et al.
patent: 5509038 (1996-04-01), Wicki
patent: 5915107 (1999-06-01), Maley et al.
patent: 6033441 (2000-03-01), Herbert
patent: 6049887 (2000-04-01), Khandekar et al.
patent: 6055285 (2000-04-01), Alston
patent: 6057789 (2000-05-01), Lin
patent: 6128749 (2000-10-01), McDonnell et al.
patent: 6163545 (2000-12-01), Flood et al.
patent: 6333646 (2001-12-01), Tsuzuki
patent: 6359479 (2002-03-01), Oprescu
patent: 6366530 (2002-04-01), Sluiter et al.
patent: 6366991 (2002-04-01), Manning
patent: 6396887 (2002-05-01), Ware et al.
patent: 6424688 (2002-07-01), Tan et al.
patent: 2002/0120902 (2002-08-01), Brown
Clifford E. Cummings; “Simulation and Synthesis Techniques for Asynchronous FIFO Design”; SNUG San Jose 2002, Rev 1.1; pp. 1-21, Apr. 19, 2002.
U.S. Appl. No. 10/402,706, filed Mar. 28, 2003, Sabih.
Behiel Arthur Joseph
King John J.
Rutz Jared
Sparks Donald
Xilinx , Inc.
LandOfFree
Systems and method for transferring data asynchronously... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Systems and method for transferring data asynchronously..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and method for transferring data asynchronously... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3612882