Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-10-27
2009-06-30
Lane, Jack A (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S155000, C711S213000
Reexamination Certificate
active
07555609
ABSTRACT:
Systems and methods are disclosed herein for retrieving data from memory in a computer system. In one example, a memory controller is coupled to a system bus in a computer system that includes bus masters similarly coupled to the system bus. The memory controller is configured to receive requests to read or write data from memory from bus masters of the computer system. If the memory controller receives an initial request from certain bus masters, the memory controller is further configured to anticipate a future request from certain bus masters and prefetch data on behalf of certain bus masters for rapid delivery following a subsequent request to read data from memory submitted by the certain bus masters.
REFERENCES:
patent: 6970978 (2005-11-01), Wu
patent: 7149850 (2006-12-01), Minami
Davis Daniel
Duncan Richard
Miller William V.
Lane Jack A
Thomas Kayden Horstemeyer & Risley
VIA Technologies Inc.
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