Systems and devices for quantum processor architectures

Details Systems and devices for quantum processor architectures Systems and devices for quantum processor architectures

2009-06-12

2011-11-22

Ismail, Shawki (Department: 2819)

Electronic digital logic circuitry

Superconductor

Tunneling device

C326S041000, C326S047000, C326S101000

Reexamination Certificate

active

08063657

ABSTRACT:
A quantum processor may employ a heterogeneous qubit-coupling architecture to reduce the average number of intermediate coupling steps that separate any two qubits in the quantum processor, while limiting the overall susceptibility to noise of the qubits. The architecture may effectively realize a small-world network where the average qubit has a low connectivity (thereby allowing it to operate substantially quantum mechanically) but each qubit is within a relatively low number of intermediate coupling steps from any other qubit. To realize such, some of the qubits may have a relatively high connectivity, and may thus operate substantially classically.

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U.S. Appl. No. 12/266,378, filed Nov. 6, 2008 in the name of Vicky Choi, 38 pages.
PCT Application No. PCT/US2009/37984, filed Mar. 23, 2009 in the name of Paul Bunyk et al., 62 pages.

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