Systems and arrangements to interconnect components of a...

Details Systems and arrangements to interconnect components of a... Systems and arrangements to interconnect components of a...

2005-06-27

2009-02-17

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S203000, C257S206000, C257S737000, C257S758000, C257S776000

Reexamination Certificate

active

07492013

ABSTRACT:
Systems and arrangements to interconnect cells and structures within cells of an integrated circuit to enhance cell density. Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted to match the pitch for the polysilicon gate. In one embodiment, the next to the lowest metallization layer running in the same orientation as the polysilicon gate, utilized to access the input or output of the interconnected cell structures is relaxed to match the minimum contacted gate pitch and the metal is aligned above each polysilicon gate. In another embodiment, the polysilicon gate pitch may be relaxed to attain a smaller lowest common multiple with the wire pitch for an integrated circuit to reduce the minimum step off.

REFERENCES:
patent: 4928160 (1990-05-01), Crafts
patent: 5341310 (1994-08-01), Gould et al.
patent: 6430733 (2002-08-01), Cohn et al.
patent: 2002/0057605 (2002-05-01), Yamakoshi
patent: 2002/0140106 (2002-10-01), Kurjanowicz

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