Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-11-29
2005-11-29
Padmanabhan, Mano (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C709S231000, C709S230000, C709S232000, C711S144000, C711S145000, C711S156000, C711S163000
Reexamination Certificate
active
06970980
ABSTRACT:
Various systems and methods for using a directory based coherency protocol in a system that employs a split ownership and access right cache coherence mechanism are disclosed. A computer system may include a directory, several active devices configured to access data stored, an address network configured to convey coherence requests point-to-point between the active devices and the directory, and a data network configured to convey data between the active devices. If at least one of a subset of the active devices has a shared access right to a requested coherency unit, the directory is configured to send an invalidating address packet to each of the active devices in the subset. The subset contains fewer than all of the active devices.
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Cypher Robert E.
Phelps Andrew
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Namazi Mehdi
Padmanabhan Mano
Sun Microsystems Inc.
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