System with intersystem information links for intersystem traffi

Details System with intersystem information links for intersystem traffi System with intersystem information links for intersystem traffi

1996-08-14

1999-12-14

Lee, Thomas C.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395287, 395685, 395840, 39580032, 711118, G06F 1300, G06F 1208

Patent

active

060028831

ABSTRACT:
The exchange of commands and data between I/O devices, such as DASDs, and a computer system, preferrably a multiprocessor computer system, usually takes place via I/O adapters. The question arises of how to couple these I/O adapters to the computer system. In prior art solutions, the I/O adapters were either attached to the second level cache or to a memory bus. The present invention relates to a method of coupling the stream of I/O commands and I/O data to the computer system via the processor busses. Because of the high bandwidth of the processor busses, an additional transmission of I/O data does not disturb regular data traffic on the processor bus. One advantage of using the processor busses for the transmission of I/O data is that pins of the second level cache chips don't have to be used for the attachment of I/O adapters any more and thus become available for other purposes. For example, the bandwidths of processor busses or memory busses can be increased, or additional processor busses can be accomodated.

REFERENCES:
patent: 5014236 (1991-05-01), Pogorzelski et al.
patent: 5241631 (1993-08-01), Smith et al.
patent: 5309568 (1994-05-01), Ghosh et al.
patent: 5426737 (1995-06-01), Jacobs
patent: 5485585 (1996-01-01), Huynh et al.
patent: 5557769 (1996-09-01), Bailey et al.

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