System verifying apparatus and method which compares...

Details System verifying apparatus and method which compares... System verifying apparatus and method which compares...

2005-11-22

2005-11-22

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06968520

ABSTRACT:
An apparatus and method which verify a system including a microprocessor. The apparatus includes first and second simulators which verify a target architecture using a test program and a functional description of the system, respectively. The first and second simlators extract first event information that expresses a verification item relating to a specification of the system. Further, checkers compare results of verification run by the second simulator with results of verification run by the first simulator. The first and second simulators execute an identification of the verification item. The checkers further examine a coverage of the system on the basis of second event information extracted from the verification item with the first event information, if the results of the verification run by the first simulator match the results of the verification run by the second simulator. The second event information is annotation data that describes information on events based on a specification for the system.

REFERENCES:
patent: 5465216 (1995-11-01), Rotem et al.
patent: 6016554 (2000-01-01), Skrovan et al.
patent: 6292765 (2001-09-01), Ho et al.
patent: 6493852 (2002-12-01), Narain et al.
patent: 6539523 (2003-03-01), Narain et al.
patent: 6591403 (2003-07-01), Bass et al.
patent: 6609229 (2003-08-01), Ly et al.
patent: 6651228 (2003-11-01), Narain et al.
patent: 6742166 (2004-05-01), Foster et al.
patent: 2002/0038203 (2002-03-01), Tsuchiya
patent: 2003/0115562 (2003-06-01), Martin et al.
X. Chen et al., Utilizing Formal Assertions for System Design of Network Processors, Proceedings of the Design, Automation and Test in Europe Conference, pp. 126-131, Feb. 2004.
J. Yim et al., Design Verification of Complex Microprocessors, Proceedings of IEEE Asia Pacific Conference on Circuits and Systems, pp. 441-448, Jun. 1996.
L-C Wang et al., A New Validation Methodology Combining Test and Formal Verification for PowerPC Microprocessor Arrays, Internation Test Conference, pp. 954-963, Jul. 1997.
J. Monaco et al., Functional Verification Methodology for the PowerPC 604 Microprocessor, 33rd Design Automation Conference, pp. 319-324, Jun. 1996.
P. Mishra et al., Automatic Functional Test program Generation for Pipelined processors Using Model Checking, Seventh IEEE International High-Level Design Validation and Test Workshop, pp. 90-103, Oct. 2002.
D.A. Wood et al., Verifying a Multiprocessor Cache Controller Using Random Test Generation, IEEE Design & Test of Computers, pp. 13-25, Aug. 1990.
You-Sung Chang et al., Verification of a MicroProcessor Using Real World Applications, Proceedings of the Design Automation Conference, pp. 181-184, Jun. 1999.
Scott Taylor et al., Functional Verification of A Multiple-issue, Out-Of-Order, Superscalar Alpha Processor-the DEC Alpha 21264 Microprocessor, Proceedings of the 35thAnnual Conference on Design Automation, pp. 638-643, May 1998.
Scott Taylor, et al., “Functional Verification of a Multiple-Issue, Out-of-Order, Superscalar Alpha Processor—The DEC Alpha 21264 Microprocessor”, 35thDesign Automation Conference, 7 pages.

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