System used to test plurality of DUTs in parallel and method...

Details System used to test plurality of DUTs in parallel and method... System used to test plurality of DUTs in parallel and method...

2006-03-14

2006-03-14

Tang, Minh N. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010

Reexamination Certificate

active

07012443

ABSTRACT:
Provided is a system and method of testing a plurality of devices under test (DUTs) in parallel. The method includes preparing at least two DUTs having input/output signal pins connected in common to one input/output signal channel and having chip selection signal pins connected to a chip selection signal channel, which provides a chip selection signal to specify one output data among output data to be outputted through the commonly connected input/output channel. The method includes reading the outputted data specified by the chip selection signal through the commonly connected input/output signal channel from one of the devices under test selected by the chip selection signal.

REFERENCES:
patent: 4244048 (1981-01-01), Tsui
patent: 4947357 (1990-08-01), Stewart et al.
patent: 5623202 (1997-04-01), Yung
patent: 5796246 (1998-08-01), Poh et al.
patent: 5994912 (1999-11-01), Whetsel
patent: 6483758 (2002-11-01), Kim et al.
patent: 2001-176293 (2001-06-01), None
English language of Abstract from Japanese Patent Publication No. 2001-176293.

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