Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-06-23
2002-03-12
Ghayour, Mohammad H. (Department: 2734)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S373000, C327S149000, C327S150000
Reexamination Certificate
active
06356610
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of communication. More specifically, the present invention relates to digital communication between digital systems.
BACKGROUND ART
There are many different electronic devices available to the general public which offer a wide variety of useful functions to their operators. Many of these electronic devices internally operate utilizing digital technology as opposed to analog technology. For example, computers, calculators, telephones, cameras, personal digital assistants (PDAs), televisions, and the like, can all internally operate utilizing digital technology. Electronic devices which utilize digital technology are sometimes referred to as digital systems. Furthermore, the digital subcomponents located within digital electronic devices are also referred to as digital systems.
Transmission of digital data between digital systems has become an essential element of commonly used systems.
FIG. 1
is a block diagram of a typical prior art digital transmission and reception system
100
. Within system
100
, digital transmitter device
102
transmits a digital data signal
106
accompanied by a clock signal
108
to digital receiver device
104
. The reason for transmitting clock signal
108
along with digital data signal
106
is to ensure stable data sampling by digital receiver device
104
. Digital receiver device
104
utilizes a data register circuit
112
to receive digital data signal
106
while utilizing a clock generator circuit
110
to receive clock signal
108
. In order for data register circuit
112
to operate properly while receiving digital data signal
106
, its input timing requirement needs to be satisfied. As such, the main function of clock generator circuit
110
is to derive a clock signal
114
from clock signal
108
in such a way that the input timing requirement of data register circuit
112
is satisfied. The input timing requirement of data register circuit
112
is described in more detail below with reference to
FIGS. 2A and 2B
.
FIG. 2A
is a block diagram of data register circuit
112
of
FIG. 1
, which is implemented as a clocked D flip-flop circuit. In order to understand the timing requirement of data register circuit
112
, it is important to first understand its basic operations. The main function of data register circuit
112
is to output the same signal value that it receives as an input signal value. But this does not occur until data register circuit
112
receives a clock signal that transitions from one voltage level to another (e.g., from 0 to 1 volt). For example, assume that input
202
of data register circuit
112
is equal to the value of 1. Upon receiving a clock signal transition
206
, data register circuit
112
causes output
204
to be equal to the value of 1.
In order for data register circuit
112
of
FIG. 2A
to function properly, there is a timing requirement that typically needs to be satisfied.
FIG. 2B
is a timing diagram illustrating the timing requirement of data register circuit
112
of FIG.
2
A. The internal circuitry of data register circuit
112
ordinarily necessitates that the data value at input
202
remain stable and unchanged during a set-up time
220
and a hold time
222
of an active clock transition
206
, which are collectively referred to as a stability window
226
. When the timing condition is satisfied, the data value at output
204
reflects the data value of input
202
during clock transition
206
, as indicated by section
228
. It should be appreciated that once clock transition
206
is received by data register circuit
112
, there is a propagation delay
224
that occurs before the data value at output
204
reflects the data value of input
202
.
There is a disadvantage associated with data register circuit
112
as described above with reference to
FIGS. 1
,
2
A, and
2
B. The disadvantage occurs when the timing requirement of data register circuit
112
is violated and clock generator circuit
110
of
FIG. 1
is unable to rectify the situation.
FIG. 2C
is a timing diagram illustrating a violation of the timing requirement of data register circuit
112
, which causes unstable data transfer and can result in a loss of data or signal distortion. As previously stated, the internal circuitry of data register circuit
112
typically necessitates that the data value at input
202
remain stable and unchanged during stability window
226
. As shown in
FIG. 2C
, the data value at input
202
does not remain stable during stability window
226
. Instead, a data transition
250
occurs at input
202
during hold time
222
, thereby violating the timing requirement of data register circuit
112
. When the timing requirement is violated, the data value at output
204
becomes unpredictable, as indicated by section
252
. In other words, the data value at output
204
could be equal to the value of one or to the value of zero, but there is no way of determining which data value. Furthermore, the violated timing requirement of data register circuit
112
could cause the data value of output
204
to exhibit the effect of metastability, meaning the data value is not equal to one or zero, but instead is some value in between zero and one. Semiconductor manufacturers have designed circuitry making the problem of metastability less significant, but within the prior art it is not totally avoidable.
Within the prior art, special circuits and technologies have been developed which improve the robustness of data register circuit
112
against such unstable operation by greatly narrowing stability window
226
and also improving its recovery properties even if stability window
226
is violated. This leads to an improvement in the reliability of digital receiver device
104
and a rare occurrence of timing violations of data register circuit
112
. However, when timing violations of data register circuit
112
do occur, they are not detected and may lead to undesirable behavior or malfunction of the whole digital receiver device
104
. Furthermore, there remains a certain residual risk of data corruption that may be unacceptable for high data rates or highly secure digital systems.
Thus, what is desired is a system which enables a digital transmitter device and a digital receiver device to communicate while avoiding unstable data transfer, which can result in a loss of data or signal distortion. The present invention provides this advantage.
DISCLOSURE OF THE INVENTION
The present invention includes a system that enables digital systems to communicate while avoiding unstable data transfer, which can result in a loss of data or signal distortion. For instance, the present invention includes a system that enables detection of potentially unstable operating conditions for a digital receiver device during its reception of clock and digital data signals from a digital transmitter device. One embodiment of the present invention monitors the received clock and digital data signals in order to detect any potential violations of the internal input timing requirement of the digital receiver device. If any potential violations of the input timing requirement are detected, the present invention invokes measures to eliminate them by manipulating the phase of the clock signal utilized internally by the digital receiver device to sample the received digital data signals. In this manner, the present invention ensures that the digital receiver device internally operates within its input timing requirement and thereby avoids unstable operating conditions which can result in signal distortion or a loss of data. Therefore, the present invention enables digital systems to communicate while avoiding unstable data transfer.
Specifically, one embodiment of the present invention is a system for avoiding unstable data transfer between digital devices, wherein the system includes a digital transmitter device and a digital receiver device. The digital transmitter device transmits a data signal and a first clock signal. The digital receiver device is coupled to rec
Ghayour Mohammad H.
VLSI Technology Inc.
Wagner , Murabito & Hao LLP
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