Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-09-12
2003-03-25
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06539537
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system synthesizer for synthesizing a circuit for performing specified behavioral operations, from a description of the behavioral operations written in a specified language, and for outputting the circuit in a specified hardware description language.
This application is based on Japanese Patent Application No. Hei 11-259518, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Recently, the scales of ICs increased, and structures have become complicated. To develop an IC, a method for automatically synthesizing a circuit using various tools is employed. The general process for developing an IC using various tools is explained with reference to
FIG. 18. A
developer makes a circuit specification (S
101
). Next, data describing behavioral operations in a specified language is produced based on the circuit specification (S
102
). The description of the behavioral operations is then converted into the HDL (Hardware Description Language) at the RT (Register Transfer) level by a behavior synthesis tool (S
103
). A logic synthesis tool converts the HDL into a net list at a gate level (S
104
). A layout tool receives the net list, and produces a mask pattern (S
105
). Using the mask pattern, exposure for producing an IC is carried out.
Further, in recent years, ICs have come to incorporate a CPU that is a master, a hardware circuit which is a slave, and an interface circuit between the master and the slave.
In these ICs, it is often the case that the interface circuit may send a command from the master CPU to the slave hardware circuit in a real-time manner. However, in some cases alternatively, the interface circuit may include a memory (RAM) that serves as a buffer, or a memory element such as a register, and may temporarily store the command from the CPU to adjust the timing for transmitting the command.
The command from the master CPU may be temporarily written in the memory element, and may be then read out by the slave hardware circuit at timing different from the writing operation to the memory element. The data from the slave hardware circuit may be written in the memory element, and may then be read out by the master CPU.
Because the memory element is provided in the interface circuit between the master CPU and the slave hardware circuit, the slave hardware circuit does not have to receive the command from the master CPU in a real-time manner. The memory element can cause a time lag between the issue of the command from the master CPU and the reception of the command by the slave hardware circuit, depending on circumstances.
In the above-mentioned steps S
102
and S
103
of describing the behavioral operations, synthesizing the behavioral operations, and outputting the result of the synthesization, an behavior synthesis tool automatically synthesizes an IC circuit from the description of the behavioral operations in a general programming language, e.g., the C language, and outputs data in a specified hardware description language.
The behavior synthesis tool realizes the entire sequence of the described behavioral operations in a single hardware circuit, but cannot assign the behavioral operations to CPU task software and to the hardware circuit. To develop a system in which a CPU (that is, software) and hardware cooperate, e.g., a single IC which incorporates the master CPU and the slave hardware circuit, or a system on a board on which the master CPU and the slave hardware circuit are provided as separate ICs, it is necessary to manually describe in the HDL at the RT level an interface circuit between the master CPU and the slave hardware circuit, which is labor-consuming work.
When developing an IC, various models of assignment of the behavioral operations to the slave hardware circuit and the master CPU are tested by comparing and estimating the processing times of the respective models. There is the problem that the sufficient number of the models of assignment cannot be tested. Further, when the specification of a system at an upper level is changed, the IC cannot be immediately coordinated. Therefore, the development of an IC takes a lot of time.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a system synthesizer, a method for synthesizing a system, and a storage medium containing a computer program for synthesizing a system, which can produce synthesized behavioral operations of an interface circuit without describing the interface circuit at the RT level when developing an IC or a system on board containing a master CPU, a slave hardware circuit, and the interface circuit between the master and the slave.
In a first aspect of the present invention, the system synthesizer is provided for synthesizing a system from a system description, the system description containing a permanent connection statement describing an access from a first circuit to a memory element in an interface circuit, and a behavioral sequential operation statement describing the operation of a second circuit which contains an access from the second circuit to the memory element in the interface circuit. The system synthesizer comprises: a separator for separating the permanent connection statement from the behavioral sequential operation statement; a determining processing unit for determining whether a variable in the system description is an interface variable indicating the memory element in the interface circuit; an interface circuit synthesizer for synthesizing the interface circuit from the permanent connection statement separated by the separator; a behavior synthesizer for synthesizing a sequential operation circuit from the behavioral sequential operation statement separated by the separator; a merging processing unit for merging the interface circuit with the sequential operation circuit via the memory element indicated by the interface variable; and a mergence result output device for outputting the system produced by the merging processing unit in a hardware description language.
Because the system description contains the description of the interface circuit between a master and a slave, the present invention eliminates the description of the interface circuit at RT level. Accordingly, the present invention easily produces the system that contains the interface circuit between the master and the slave, a CPU that is the master and a hardware circuit that is the slave.
Thus, when estimating assignment of behavioral operations to hardware and software, a number of models of assignment can be tested. Further, when the specification of the upper level system is changed, the system can be immediately coordinated.
In a second aspect of the present invention, the separator separates the system description into the permanent connection statements and the behavioral sequential operation statements, based on the presence or absence of a specified sign in the respective statements.
In a third aspect of the present invention, the determining processing unit determines a variable, which is contained in both the permanent connection statements and the sequential statements, as the interface variable.
In a fourth aspect of the present invention, the behavior synthesizer allows the variable, which was determined as the interface variable by the determining processing unit, to exclusively use one memory element.
In a fifth aspect of the present invention, the system synthesizer further comprises an interface constraints priority information storage device for storing a priority of the first circuit or the second circuit to write data in the memory element. The merging processing unit merges the interface circuit with the sequential operation circuit so that data is written in the memory element according to the priority.
In a sixth aspect of the present invention, a clock to be supplied to the memory element is specified, based on the clocks for driving the first circuit and the second circuit.
In a seventh aspect of the prese
Maruyama Yuichi
Nakamura Atsushi
Wakabayashi Kazutoshi
Foley & Lardner
Levin Naum
NEC Corporation
Siek Vuthe
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