System storing plural I/O arrangement information wherein each I

Details System storing plural I/O arrangement information wherein each I System storing plural I/O arrangement information wherein each I

1998-03-12

2000-09-26

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

710 2, 710 3, 710 8, 710 15, 710 16, 710 17, G06F 1314

Patent

active

061254118

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to an electronic computer system which is able to use a plurality of input-output arrangement information in a single system at the same time.


BACKGROUND ART

In a present computer architecture, it is customary that a hardware executes a control concerning input-output processing such as a selection of an input-output path (channel path) up to an input-output unit (I/O) or a queue processing executed when a channel path is in use.
Under such computer architecture, the input-output processing in the electronic computer system specifies a channel path through which an instruction processor (IP) and an input-output processor (IOP) of the electronic computer system reaches the I/O and an I/O based on input-output arrangement information previously created in response to the system arrangement, and executes an input-output operation.
Heretofore, in such an electronic computer system, there has been set one input-output arrangement information for one system. Then, an upper limit of the number of input-output arrangements defined by this input-output arrangement information is previously determined from a standpoint of a computer architecture. Accordingly, the electronic computer system executes processing by using input-output arrangements that can be defined by one input-output arrangement information.
When a plurality of operating systems (OS) are operated in such an electronic computer system, a processor resource within the system is divided logically thereby to operate each OS. In this case, since the hardware for executing the input-output processing defined by the input-output arrangement information also is divided and distributed, each OS can monopolize only a part of the input-output arrangement defined by the input-output arrangement information. In addition, since the number of input-output arrangements that can be defined by the input-output arrangement information is limited, even if the number of the input-output arrangements of the electronic computer system increases, the increased input-output arrangements cannot be supported, which becomes a factor that limits the data processing capability.
As a means for solving the aforementioned problem, to known that the hardware of an electronic computer system can be physically divided, whereby one electronic computer system is operated as two electronic computer systems which are made independent physically.
FIG. 1 is a block diagram showing an electronic computer system obtained in such an operation mode. In FIG. 1, reference numerals 1, 2 denote two electronic computer systems which are made independent respectively.
FIG. 2 is a block diagram specifically showing the electronic computer system 1 in FIG. 1. In FIG. 2, the electronic computer system 1 comprises an instruction processor (IP) 11, a main storage (MS) 12, a service processor (SVP) 13, an input-output processor (IOP) 14 and a system controller (SC) 15 which combines these processors 11, 13, 14 and the MS 12. The IOP 14 includes channels CH 141, 142, 143, 144 which are controlled by the IOP 14. An input-output unit (I/O) 16 is connected to the channels CH 142, 143. The MS 12 includes a control information storage area 120. In the control information storage area 120, there is stored input-output arrangement information 17 inherent in the electronic computer system 1 which contains information specifying a channel path ranging from the IP 11 to the I/O 16 and information specifying the I/O 16.
When a data fetch request, for example, is issued from the OS 18 to the I/O 16, the IP 11 instructs a data fetch to the IOP 14. The IOP 14 specifies the I/O 16 with reference to the input-output arrangement information 17, selects either the channel CH 142 or the channel CH 143 which is connected to the I/O 16, and fetches data by activating the I/O 16 through the selected channel CH.
This is also true in the electronic computer system 2.
When one electronic computer system is operated as the two electronic computer systems which are made independent phy

REFERENCES:
patent: 5414851 (1995-05-01), Brice, Jr. et al.
patent: 5572694 (1996-11-01), Uchino
patent: 5600805 (1997-02-01), Fredericks et al.
patent: 5640603 (1997-06-01), Meritt et al.
patent: 5717950 (1998-02-01), Yamaguchi et al.

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