System speed loading of a writable cache code array

Details System speed loading of a writable cache code array System speed loading of a writable cache code array

1998-02-19

2000-08-15

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

712217, 711134, G06F 1300, G06F 928

Patent

active

061051098

ABSTRACT:
SMP computers systems can add to the first level cache a fill mode latch and achieve straightforward, high-performance loading of a writable cache code array that is part of a hierarchical cache structure.A new code array's write control elements include a control latch called "fill mode" for the BCE controls which when fill mode is active, then a disable is also active, since reads of the code array may not give accurate data when the array is not yet filled-up/fully valid. New mode follows the sequential steps which process code by:

REFERENCES:
patent: 5790844 (1998-08-01), Webb et al.
patent: 5802359 (1998-09-01), Webb et al.
patent: 5822558 (1998-10-01), Tran
D.C. Wong et al., "A Software Approach To Avoiding Spatial Cache Collisions In Parallel Processor Systems", IEEE Transactions on Parallel and Distributed Systems, vol. 9, pp. 601-608, Jun. 1998.
"A High-Frequency Custom CMOS S/390 Microprocessor", Charles Webb et al., IBM Journal Research and Development, pp. 241-246, 1997.
"IBM's S/390 G5 Microprocessor Design", Slegel et al., IEEE Micro, pp. 12-23, 1999.

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