Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
2000-06-29
2004-04-20
Elamin, Abdelmoniem (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S108000, C710S108000, C710S120000
Reexamination Certificate
active
06725301
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an improved data processing system and, in particular, to an improved peripheral component interconnect (PCI) bus architecture. Still more particularly, the present invention provides a method and apparatus for allowing a 64-bit PCI adapter to determine whether it is in a 32-bit or 64-bit slot during reset.
2. Description of Related Art
According to the PCI specification, version 2.1, a 64-bit adapter can operate in either a 64-bit slot or a 32-bit slot. To determine the data width of the slot in which the adapter is located, the adapter samples the REQ64# signal. A signle-line bus provides the REQ64# signal to adapters in 64-bit slots. When asserted by the system host bridge, the REQ64# signal indicates that the slot is a 64-bit slot. When asserted by an adapter located in a 64-bit slot, the REQ64# signal indicates that the adapter is operating at a 64-bit data width. As discussed below, problems arise during reset, when the REQ64# signal is not properly established. During reset, when the reset signal (RST#) is asserted, a 64-bit adapter must determine whether it is located in a 32-bit slot or a 64-bit slot. To determine the data width of the slot in which the adapter is located, the adapter samples the REQ64# signal at the end of reset, just prior to RST# being deasserted. The adapter may have no way of knowing if it is located in a 32-bit or 64-bit slot before the end of reset, because the REQ64# signal is not required to be in the proper state until ten clock cycles before the end of reset. This sequence is stated in the PCI 2.1 specification: “at the end of reset, the central resource controls the state of REQ64# to inform the 64-bit device that is connected to a 64-bit bus. If REQ64# is deasserted when RST# is deasserted, the device is not connected to a 64-bit bus. If REQ64# is asserted when RST# is deasserted, the device is connected to a 64-bit bus.” See PCI 2.1 specification, section 3.10.
The PCI specification also states that when a 64-bit device is in a 32-bit slot, the “PCI component is responsible to insure that its inputs do not oscillate and that there is not a significant power drain through the input buffer. This can be done in a variety of ways: e.g., biasing the input buffer; or actively driving the outputs continually.” See PCI 2.1 specification, section 4.2.1.1. This means that when a 64-bit adapter senses that it is in a 32-bit slot, it is responsible for not allowing the upper thirty-two bits to float. The floating pins would cause a power drain, which will result in the drivers being damaged in most cases depending on exposure time. However, the specification does not address the steps the 64-bit adapter should perform before it has a chance to determine the data width of the slot in which the adapter is installed. When the adapter is in a 32-bit slot and the adapter does not bias or drive its 64-bit extension pins bits, they will be floating during reset.
Some adapters attempt to remedy the above-mentioned problems by sampling REQ64# throughout reset. As a result, the adapter knows the data width of the slot in which it is located at the beginning of reset. However, one situation that may cause problems is when a 64-bit adapter is installed in a 64-bit slot. The 64-bit adapter could see the REQ64# signal deasserted at the beginning of reset, and the 64-bit adapter will drive its 64-bit extension pins as if it were in a 32-bit slot. However, the system host bridge is required to drive the bus during reset, so two devices would be driving the bus at the same time. The bus is referred to as being in contention if the adapter and the system host bridge are driving at different levels. Bus contention results in “crowbarring,” which causes a large amount of current to flow through the bus, increasing the potential for device failure due to over-current component driver stress.
Hence, it would be advantageous to allow 64-bit PCI adapters to determine the type of slot in which it is installed from the beginning of reset.
SUMMARY OF THE INVENTION
The present invention solves the problems of the prior art by modifying the planar on systems that have a REQ64# signal to indicate 64-bit slots on a bus. The present invention causes the REQ64# signal to be asserted when the adapter is in reset on a 64-bit slot. This allows the adapter to see that it is in a 64-bit slot at the beginning of reset, preventing the adapter from driving the 64-bit extension pins.
REFERENCES:
patent: 5948090 (1999-09-01), Heinrich et al.
patent: 6128682 (2000-10-01), Humpherys et al.
patent: 6189058 (2001-02-01), Jones, III et al.
Gholami Ghadir Robert
McLaughlin Mark David
Upton John Daniel
Elamin Abdelmoniem
McBurney Mark E.
Tkacs Stephen R.
Yee Duke W.
LandOfFree
System solution to allow 64-bit PCI adapters to determine... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System solution to allow 64-bit PCI adapters to determine..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System solution to allow 64-bit PCI adapters to determine... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3221846