Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-04-09
2001-02-06
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
06185704
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates in general to computers and, more particularly, to computer memory modules.
2. Description of the Related Art
Over the last few years, the operation of the personal computer has become more oriented toward multimedia operation. Multimedia computers typically include a mass storage device with a replaceable medium, such as a CD-ROM (compact disk read only memory) or a DVD (digital versatile disk), a sound card with a FM synthesis or wave table generation processor, real-time video capabilities and three dimensional graphics. Other multimedia capabilities, such as speech synthesis and voice recognition, are becoming more mainstream as the power of the computers increase.
Multimedia capabilities such as sound, video, fax, modem, compression and decompression, however, are resource intensive. Some features are bandwidth limited, meaning that the features cannot be expanded without increasing the bandwidth of the system buses. In a typical IBM-compatible PC, the ISA (industry standard architecture) bus runs at eight megahertz (16 bits) while the PCI (Peripheral Connect Interface) bus runs at thirty-three megahertz (32 bits). Other features are processor limited. In a multitasking computer system, the main processor can be responsible for a number of activities. Therefore, multimedia features which require a large number of processor instruction cycles can slow down the system or not execute properly. Still other multimedia features are memory limited. These features require a large amount of memory in order to execute. Large memories lead to increased system cost.
For example, modem features like V.34bis are primarily processor limited. Wavetable synthesis requires large amounts of memory and is memory-limited. Decompression feature like MPEG2 is compute-limited as well as bandwidth limited. With increasing clock-speeds of Intel CPUs, some of these can be executed on the host CPU. But this loads the host CPU with fewer MIPS (million instructions per second) available for the user application. Increased clock speeds also lead to increased power consumption and reduced battery life.
One popular approach is to provide these functions in a desktop computer using multiple add-in ISA or local bus cards. These add-in cards are host dependent and cannot be used on multiple platforms. For example, an ISA card cannot work on a Sun workstation or a Macintosh. Notebook computers, palmtops and PDAs (personal digital assistants) have no space for such ISA cards. And they all suffer from the classic Von Neumann bottleneck—the CPU-Memory bandwidth limitation.
Processor technology has focused on improving raw processing speed. As an example, the instruction cycle time of a recent digital signal processor design in the TMS320 family, by Texas Instruments Incorporated of Dallas, Texas, is 5 ns (nanoseconds), as compared to the cycle time of 200 ns in the first generation. As long as the computations are on-chip, these devices provide adequate throughput. But several applications in speech, signal and image processing are memory intensive and the gain in raw processing speed is lost when the processor has to fetch and process data from slower off-chip memories. The combined effect of decreasing cycle time of processors and increasing density of memory devices is further aggravating the CPU-to-memory bandwidth—a paramount issue in computer system design.
As computers evolve from desktop size to laptop, notebook and palmtop sizes, form factor and power consumption become critical. Laptops are expected to have the capability of a desktop as users demand more functionality.
Multiprocessing promises great potential for increasing the throughput of systems as the limits of decreasing the cycle time of uniprocessor systems are approached. But multiprocessing has not yet proliferated, primarily because of the “processor-driven” approaches and the difficulty in designing systems, developing communication protocols, and designing software support routines. Application partitioning is a major problem because it requires a detailed understanding of the application that is being accelerated. Software development methodologies and partitioning tools are still in their infancy. In addition, there is no standard way of connecting two or more processors.
Accordingly, a need has arisen for a method and apparatus for providing flexible, compatible processing for multimedia and other resource intensive features.
BRIEF SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, the present invention provides a memory module comprising a semiconductor memory and one or more processors coupled to the semiconductor memory on an integrated module. Circuitry on the integrated module provides communications between system processing circuitry and the processor, such that said system processing circuitry can access the semiconductor memory as main memory and can instruct the processor to transform data and store transformed data in said semiconductor memory for access by the system processing circuitry.
The invention provides significant advantages over the prior art. Adding a digital signal processor to a computer system to enable enhanced functions is as easy as expanding the memory of a MPU (main processing unit). The memory module can use a form factor of the type standardized by organizations like IEEE, JEDEC, and so on, such as a SIMM (single in-line memory module) or DIMM (dual in-line memory module) form factor.
Different applications may be downloaded by the MPU to the memory module for local execution. The memory module therefore supports multiple functionality, i.e., downloadable, multiple functions under software control of the MPU.
The DSP/memory module offers the highest possible bandwidth between the MPU and coprocessor at any given time and technology. The DSP/memory module is both bus-independent, and host-independent, for use with PCs (personal computers), PDAs (personal digital assistants), workstations and other computer systems.
The DSP/memory module reduces system cost by sharing system memory over a number of multimedia functions.
The module provides a framework for easily scaling up the processing power of a computer system; an existing single processor system can be transformed into a scaleable, multiprocessing system simply by adding a memory module
Users do not have to change their product platforms in order to get/offer new, value-added functions. Adding the DSP/memory module and software can allow users to increase the capability of their computers.
In accordance with other embodiments of the present invention, implementation of the memory module with the interrupt request, IREQ, and WAIT signals are described further in this application. Six options are presented in accordance with other embodiments describing how to implement these signals (including their timing and relation to the host memory controller).
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Heape Judd E.
Iwata Yoshihide
Mahlum Douglas L.
Pawate Basavaraj I.
Reuter Fred J.
Chung Phung M.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Troike Robert L.
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