System-on-chip power reduction through dynamic clock frequency

Details System-on-chip power reduction through dynamic clock frequency System-on-chip power reduction through dynamic clock frequency

2004-05-13

2009-12-29

Du, Thuan N (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S321000, C713S501000, C713S503000, C710S107000

Reexamination Certificate

active

07640446

ABSTRACT:
A dynamic clock frequency module for a system-on-chip (SOC) including modules that communicate over a system bus includes a request evaluation module that receives requests to utilize the system bus from the modules. A frequency assignment module calculates a clock frequency value for the system bus based on the requests received by the request evaluation module. The request evaluation module includes a summing module that generates a sum of requests between the modules. A pulse stretch module increases a period of time that at least one of the requests is asserted. A low pass filter prevents changes to the clock frequency value when the sum at least one of increases and decreases for less than a predetermined period. A slew rate control module adjusts at least one of a rate of increase and a rate of decrease in the clock frequency value.

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